Research On Media Enhanced Digital Signal Processor Core Design For System-On-Chip

How to utilize the available hardware resources on the silicon chip effectively is a key issue in high performance/cost media system-on-chip (SoC) development. A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware IP cores and one or more on-chip memories usually provides a good solution. The research work introduced in this paper mainly concerns the processor core design for media SoC.Media enhancement backward extension to MIPS-I compatible ISA is presented in this paper. Based on the analysis of inherent characteristics of media application algorithms, the basic MIPS-I compatible ISA is extended to support sub-word parallel SIMD operation, special result handling, and dedicated media instructions. The media enhancement extension to MIPS-I compatible ISA is physically realized in the processor core, and improves media processing performance effectively (2-4x) with negligible additional hardware cost (2.7%).A Finite State Machine (FSM) based centralized control scheme is presented in this paper to supervise the CPU pipeline activity. And some effective techniques are discussed to lower the clock period and CPI (Cycles Per Instruction) of the pipeline. To eliminate the clock frequency limitation by some complex instructions' long executing time and achieve single-cycle throughput, a scalable super-pipelining extension technique together with a high performance/cost pipeline shift mechanism is presented in this paper. For single-issue processor architecture, the radical solution to CPI reduction is to decease pipeline stalls exploiting available software or hardware techniques. A RAW (Read After Write) dependency loop model is developed in this paper to analyze the RAW hazards of register operands in complex pipeline. Based on this model, a "dynamic" data forwarding policy is suggested to reduce the pipeline stalls caused by data RAW hazards. Theoretical analysis and practical experiments both show that the average CPI increment caused by data RAW hazards can be reduced effectively by the dynamic data forwarding strategy.Bus design and media data stream scheduling are key issues in real-time media SoC development. Data scheduling policies for MPEG-1/2 video decoding is discussed in this paper according to software or hardware implementation case. Two 3-frames-grained scheduling policies are suggested to make good trade-off between processing demands and on-chip buffer demands in software decoding implementation. A static time division multiplexed scheduling / dynamic fixed priority arbitration based 2-level hybrid arbitration scheme, incorporated with synchronization control, is introduced in this paper to utilize the bus bandwidth effectively and lower on-chip buffer demands in media SoC.