Research On Interconnect Driven Floorplanning Algorithms For System On Chip

IP cores are widely used in System on Chip (SOC) design, which imposes ahierarchical methodology and introduces new requirements to the interconnect op-timization of the floorplanning algorithms. Moreover, due to the growing needs forthe system communication, traditional bus structure is stepping into Network on Chip(NOC), which introduces new challenges to the floorplanners as well. Facing thesenew requirements and challenges, this paper handles general on-chip interconnectionsduring the floorplanning stage in SOC scenario. Then, for the specific interconnec-tions such as buses and NOC, floorplanning is invoked with other stages and twospecific algorithms are implemented respectively for bus and NOC optimization.Contributions are briefly previewed as follows:1For the general interconnections in SOC design, a new fixed-outlinefloorplanner is proposed. The idea of solving a group of equations is iterativelyapplied in the floorplanning algorithms for the first time. It provides high-qualityfloorplans in each iteration step of Simulated Annealing (SA) with high efficiency.Compared with six state-of-the-art floorplanners, our algorithm can satisfy the tightestfixed-outline constraint and achieve the shortest total wirelength. Furthermore, mixeddesigns with both hard and soft modules are well settled. In addition, the runtime iscomparable with the other previous SA-based floorplanners.2If the chip wirelength is similar, buffer insertion is an important way tofurther reduce the interconnect delay. According to our observation, the success rateof buffer insertion is determined by both topological and geometric structures.However, previous works only considered one of them. In this paper, an existingfloorplanning algorithm named Least Flexibility First (LFF) is revisited to considerboth structures at the same time. Compared with previous work, the success rate ofbuffer insertion is improved by more than30%, yet with similar area and wirelength.3When the communication volume increases, bus routing becomes thebottleneck of the system interconnections. A post-floorplanning procedure isdeveloped and some incremental revisions are performed on the existing floorplan, inorder to make all the modules comply with the constraints of bus routing and thusimprove the performance of the buses. Compared with the latest previous work whichconsidered bus routing during floorplanning, our post-floorplanning method is19 times faster with similar optimization results on the chip area and wirelength.4Another therapy is NOC since the bus routing becomes the bottleneck.Tile-based NOC, which is commonly accepted by the industry, is studied in thefloorplanning stage. Different from the traditional floorplanning problem, Tile-basedNOC only allows the modules to be placed right on these tiles instead of everywhereon the chip. Besides, the performance of the on-chip networks is partially decided byHigh Level Synthesis (HLS) as well. Therefore, Mixed Integer Linear Programming(MILP) is adopted as a unified model combining tile-based floorplanning andhigh-level task scheduling. Besides, a linear metric using Labeled Graph is alsointroduced into MILP to estimate the performance and energy of the networks.According to the simulation results, our unified model improves both the performanceand energy by more than10%on most benchmarks, compared with previous works.