Design Of Software And Hardware Co-testing System For SIP

With the development of integrated circuit industry,various new chips emerge one after another.Among them,System-in-Package(SIP)chips have been widely applied due to the advantages of high integration and strong compatibility.In chip testing,due to the heterogeneous integration of SIP chips,there are many difficulties in the current testing of SIP chips,such as the difficulty in fault diagnosis of internal components,the complex testing process and the difficulty in system performance evaluation.Therefore,how to effectively diagnose faults and test the performance of SIP chips has become the urgent problem.In this thesis,a domestic general signal processing SIP chip is taken as the test object,and the test research is carried out.By developing a board-level test system with software and hardware cooperation,the function and performance test of the internal storage components of the SIP chip under test and the performance test of the external interface of the chip are realized,and finally the component fault diagnosis and chip performance evaluation are realized.The main research contents of this thesis are as follows:(1)Improvement of board-level test system structure.Firstly,by analyzing the resource characteristics of the SIP chip to be tested and the typical failure model of SIP,the test requirements of the chip are analyzed.Then,according to the characteristics of So C components of the chip under test,the original board-level test system structure is improved,and the board-level test system structure with software and hardware cooperation is proposed,which reduces the system cost and the development difficulty.(2)Design of software and hardware collaborative testing system.The hardware design needs to meet the power supply requirements,communication interface requirements and test requirements;The software design of the test system is completed on the PC side and the ARM side of the chip to be tested,which realizes the functions of TCP protocol communication between the chip and the PC,test data collection and transmission,and user UI interface.(3)Test program design.Programming the FPGA+ARM architecture in the SIP chip to be tested,completing the test program design,realizing the function and performance test of DDR3,Nor Flash and e MMC,the performance test of external interfaces RGMII,LVDS and GTX,and the performance test of CPU.The test data is received,processed and displayed by the upper computer software.In this thesis,a board-level test system with software and hardware cooperation for MSXXXXZZ chip is designed,and the three-temperature test data of the first batch of chips are successfully collected.According to the theoretical parameters,industry standards and failure analysis images,the test data are analyzed and compared,the chip fault diagnosis and performance evaluation are effectively completed.This thesis establishes the test technology platform for ZYNQ+ memory SIP chip.