OTFS System Technology Research And IP Core Design

With the continuous development of wireless communication,providing high-speed,highquality,low-latency,and low-energy wireless communication for high-speed mobile users has become the development trend of future mobile communication technology.Compared with Orthogonal Frequency Division Multiplexing(OFDM),Orthogonal Time-Frequency-Space(OTFS)modulation can show better perception performance and Doppler shift suppression performance in high-speed scenarios.At present,relevant research has been done on the theoretical performance and simulation of orthogonal time frequency space(OTFS)modulation technology at home and abroad,but there is still no breakthrough in the research and scheme of OTFS transmitting receiver.The main reason is that the high complexity of algorithm makes the hardware design more difficult.Based on the above background,this dissertation had studied the low complexity OTFS detection algorithm in the high-speed mobile scene,put forward a suitable OTFS digital baseband link model and hardware IP core design scheme.Firstly,aiming at the problem of high complexity of OTFS signal detection algorithm,this dissertation constructed a matching filter based on the characteristics of OTFS channel matrix.On the basis of Generalized Approximate Message passing(GAMP)Algorithm,the dissertation had proposed a damping generalized message passing algorithm based on expectation maximization(EM).Compared with traditional message passing(MP),approximate message passing(AMP),GAMP and other detection methods,the proposed scheme has lower complexity.Simulated in a highly dynamic scenario of 500km/h,the bit error rate performance is better than the minimum mean square error(MMSE)and traditional GAMP detection algorithms,and it has better convergence.On this basis,the dissertation analyzed the hardware design of the EMD-GAMP algorithm.Under the premise of not affecting the bit error rate,the channel matrix is transformed into the real number domain at first,and then reduces the resource occupation of the multiplier in the hardware calculation.A reasonable hardware storage structure is proposed for a large number of matrix vector operations in the algorithm,and the RTL code is designed for the hardware modules in turn.The algorithm is simulated and integrated on Vivado development platform,and verified on board based on the existing XC7A200 T FPGA.Finally,the signal detection function under different noise power is realized.Secondly,according to the proposed OTFS digital baseband link architecture,the IP core of the transmitter signal source preprocessing module is designed,and the conversion from random bit stream to OTFS data frame is successfully realized.In addition,the dissertation had completed the IP core design of OTFS modulation and demodulation module based on FPGA,and designed a data transmission interface with configurable symbol number and subcarrier number,and conducted demodulation at the receiving end to compare and analyze the bit error rate of the results.Finally,this dissertation analyzed the advantages of RISC-Ⅴ E203 CPU,which is currently open source,and successfully ports and verifies the interface of the CPU in XC7A200 T FPGA.The OTFS digital baseband link based on E203 CPU was built on Vivado platform and verified by simulation.In the early research and development stage of OTFS transmitting receiver,the method described in this dissertation can accelerate the development progress of digital baseband link,and provide a good reference for the design of OTFS principle prototype.