Neural Network Accelerator Based On ReRAM Non-volatile Memory

The rapid development of machine learning and artificial intelligence in the past decade has brought tremendous changes in all aspects of human life.In particular,artificial neural networks have achieved unprecedented success in image recognition,language process,and intelligent decision-making.The computational complexity of neural network training and inference increases with more extensive networks,putting forward higher hardware computing efficiency requirements.However,traditional Von Neumann architecture processors(CPU and GPU)inevitably encounter data transfer bottlenecks separated by memory and computing unit.To solve the memory wall problem,compute-in-memory architecture based on non-volatile memory has become a research hotspot in recent years.ReRAM,composed of memristors,is a new type of nonvolatile memory,and researchers often use it to design compute-in-memory accelerators.The artificial intelligence hardware architecture based on ReRAM is expected to become the next generation of novel high-performance hardware processors.Therefore,under the above background,the main research contents of this thesis are the ReRAM circuits design,ReRAM compute-in-memory architecture design,and hardware acceleration of neural networks based on ReRAM.The works of this thesis mainly include the following aspects:16Kb ReRAM memory chip design and handwriting recognition verification.The 32×32 ReRAM array and read/write driver circuits are designed,and 16 ReRAM arrays are integrated into one memory chip.Row and column decoders and sense amplifiers are arranged outside the arrays.The chip employs 180nm CMOS/ReRAM hybrid technology to tape out.In addition,a verification board for the ReRAM memory chip is developed to verify the read and write functions of the chip,and the average read and write accuracy is 99.51%.In addition,a handwriting recognition verification platform based on the ReRAM memory chip verification board,combined with Zynq-7000 FPGA equipped with a binary convolutional neural network,was built.The binary convolutional neural network weights are written into the ReRAM memory chip.Finally,the recognition of the MNIST handwriting dataset is successfully completed.Design of 128Kb ReRAM compute-in-memory architecture.A row decoder that is more flexible with extenders and a two-bit current-mode sense amplifier(2b-CSA)are designed to execute the two-row in-memory computing in the ReRAM array.The 2bCSA can read the accumulated current of two ReRAM cells and generate 2-bits output voltage signals.Compared with the traditional single-bit CSA,the throughput of 2bCSA is doubled,the access time is reduced by 70%,and the energy consumption per bit operation is reduced by 45%.Hardware optimization of LSTM network and speaker recognition hardware deployment based on 128Kb ReRAM compute-in-memory architecture.This thesis converts all floating-point calculations in LSTM network inference to fixed-point calculations utilizing quantization and fitness of the tanh activation function.The total network parameter storage is 94.7Kb,which is fully stored in the 128Kb ReRAM compute-inmemory architecture.The simulation verifies the speaker recognition function based on the TIMIT speech library.Compared with LSTM network accelerators based on FPGA,MRAM,and ReRAM,this architecture has lower power consumption and higher energy efficiency ratio.