Design And Optimization Of Stacked DBC Hybrid Packaging Structure For SiC Power Devices

As silicon carbide(Si C)power devices move towards high power and high integration,traditional packaging structures have gradually failed to meet their performance requirements.The stacked DBC(Direct Bonded Copper)hybrid packaging structure provides a new solution for the packaging of Si C power devices with low parasitic inductance and good stability.However,the stacked DBC hybrid packaging structure still faces issues such as poor thermal performance and incomplete optimization of circuit parasitic inductance.Further optimizing the thermal performance and parasitic inductance of the stacked DBC hybrid packaging structure is of great significance.This study focuses on the stacked DBC hybrid packaging structure,and analyzes the thermal performance and low parasitic inductance optimization solutions from two aspects:packaging structure and packaging materials.The specific research results are as follows:(1)The thermal characteristics of the stacked DBC hybrid power module are optimized.Based on the principle of mutual inductance cancellation,the stacked DBC hybrid packaging structure is designed.Then,the packaging structure is modeled and thermomechanical simulation analysis is carried out to study the effects of factors such as DBC substrate and solder layer on the thermal characteristics of the packaging structure.The packaging structure parameters and material parameters are obtained by comprehensively analyzing the thermal characteristics.Finally,to verify the influence of the layout of power chips on the overall thermal performance,two sets of experimental samples are designed,and the temperature of the samples is compared through experiments.The experimental results show that when the chip is located on the lower DBC,the thermal resistance is relatively small,and the thermal performance of the power module is better.(2)A new DBC+IBP stacked hybrid packaging structure is proposed on the original stacked DBC hybrid packaging structure to further optimize its thermal performance.In the new scheme,an Integrated Base Plate(IBP)is used to replace the lower DBC substrate,solder layer 2,and heat sink of the original structure.After optimization,the number of thermal interface layers between the power chip and heat sink is reduced from 7 to 5.The results show that the thermal resistance of the optimized structure can be greatly reduced,and the chip junction temperature and maximum thermal stress of the stacked DBC hybrid packaging structure are improved.(3)The optimization of parasitic inductance of the hybrid power module is studied.Ansys Q3 D simulation is used to analyze the effects of wire bond structure,power terminals,and DBC substrate on the stacked DBC hybrid packaging structure.The results show that the parasitic inductance of the circuit increases with the distance of the wire bonding point,decreases with the increase of the wire bonding diameter and the number of wire bonding on each chip;the parasitic inductance introduced by the terminals increases with the increase of the distance between the positive and negative power terminals;the increase of the width and via hole diameter of the DBC substrate leads to a decrease in the module’s parasitic inductance,while the increase in the length of the DBC substrate and the thickness of the ceramic layer leads to an increase in the module’s parasitic inductance.Finally,considering the requirements of thermal performance and low parasitic inductance,the optimal design parameters of the module are obtained.The research results of this paper provide a feasible design solution for efficient heat dissipation and low parasitic inductance of Si C power devices,and an effective analysis method for the optimization of Si C power devices.