Effects Of Traps On Electrical Properties Of HfO₂-based FeFET Device

Ferroelectric field effect transistors（FeFETs）have the advantages of simple structure,non-destructive readout and low operating voltage,making them very promising for applications.The doped HfO₂ films still have good ferroelectric properties at thicknesses as thin as a few nanometers and are compatible with complementary metal-oxide-semiconductor（CMOS）processes,enabling HfO₂-based FeFETs to meet the development needs for high integration and high performance of electronic devices.With the development of integrated circuit technology,when the size of traditional planar CMOS devices is shrinking,the effect of short channel effect on the electrical performance of devices becomes more and more serious,and the FinFET device structure can solve this problem well.One of the many obstacles encountered on the road to commercialisation of HfO₂-based FeFET-type ferroelectric memories is the poor fatigue resistance performance of HfO₂-based FeFETs.The mechanism affecting the fatigue resistance performance of FeFETs is mostly thought to be charge injection,which means charge trapping within the gate insulation layer and the generation of interfacial trap charges.With the increase of device cycles,the trap concentration inside the device increases,charge injection intensities,leading to the deterioration of fatigue performance of the device.Therefore,it is necessary to understand the mechanism of the influence of traps on the electrical performance of HfO₂-based FeFETs.In this thesis,the traps in HfO₂-based FeFET devices was simulated using Sentaurus TCAD simulation software.Due to the limitations of the Sentaurus TCAD ferroelectric model,the effect of traps on domain pinning in ferroelectric layers was not considered.The main findings and results are as follows.（1）The effects of traps in ferroelectric layer on the electrical performance of HfO₂-based FeFET devices were investigated.By analyzing the transfer characteristic（I_D-V_G）curves of HfO₂-based FeFET devices,it was found that the increase of the acceptor traps causes a shift of the I_D-V_G curve to the right and the increase of the donor traps causes a shift of the I_D-V_G curve to the left when the traps concentration vary from 0 to 1×10¹⁹ cm^-3.By comparing the memory windows of the device,it was found that the device memory window after the injection of acceptor traps is slightly smaller than the initial memory window,but the opposite was found after the injection of donor traps.When the acceptor/donor traps simultaneously acts on the ferroelectric layer,the I_D-V_G curve causes a shift to the left and the memory window increases.The above results show that donor traps in the ferroelectric layer have a more significant effect on the electrical performance of HfO₂-based FeFET devices compared with the acceptor traps.（2）The effects of Si-SiO₂ interface traps on the electrical properties of HfO₂ based FeFET devices were investigated.Through the characterization of the I_D-V_G curve of HfO₂-based FeFET device,it was found that the slope of the I_D-V_G curve would be reduced by acceptor/donor traps at the interface.The acceptor traps would decrease the on-state current,off-state current and memory window of the device,while the donor traps would increase the off-state current and decrease the memory window of the device.The electrical properties of HfO₂-based FeFET devices vary changed more obviously when acceptor/donor traps are present at the interface simultaneously.