Accelerated Optimization And Implementation Of Convolutional Neural Network Based On FPGA

With the rapid development of science and technology,deep learning has shown amazing performance in various fields.Deep Convolution Neural Network(DCNN)is one of the key technologies of deep learning.It has been widely used in target detection,object recognition,natural language processing,target classification and other fields.Nowadays,the number of DCNN layers is deeper and deeper,and the number of parameters is more and more.Limited by the memory size and computing resources of Field Programmable Gate Arrays(FPGA),DCNN is difficult to run on FPGA.Therefore,we need to design a real-time processing system with small size,low power consumption,high speed and high precision to meet the application requirements.In view of the above problems,The thesis puts forward some improvement methods by analyzing and summarizing the existing DCNN.In the aspect of network structure improvement,The thesis adopts three novel methods: MLP convolution(MLP conv)structure,step by step substitute pooling and global average pooling substitute the first layer full connection.which significantly reduce the amount of parameters and calculations.And our model is more suitable for acceleration on FPGA,The optimized network model is named Lightweight Assembled Convolutional Neural Network(LACNN).When implementing DCNN model on FPGA,The thesis adopts some optimization methods,such as convolution layer parallel acceleration,output data reuse,data pipelining and parallelization,to solve the problem that the internal resources of single FPGA are limited,which makes it impossible to realize the parallel acceleration of the whole network in FPGA.Basing on the summary and analysis of the existing related research,The thesis proposes a small and efficient network model suitable for FPGA application,which improves the efficiency of model acceleration on FPGA and saves computing resources and storage space:(1)A lightweight DCNN network is designed.Compared with the traditional DCNN,the network greatly reduces the amount of parameters and calculation on the premise of ensuring the accuracy.The network designed in The thesis integrates the methods of sub network embedding,step replace pooling,average pooling replace full connection,and uses tensorflow to complete the construction of network model.The classification accuracy of the network on Flower＿photos data set is 88.6%,which is almost the same as VGG16.The amount of parameters is only 1/140 of VGG16,and the amount of calculation is 1/24 of VGG.Compared with VGG,the network achieves higher classification accuracy with minimal amount of parameters and calculation.(2)Realize the optimization and acceleration of the above network on FPGA.In view of the shortcomings of traditional DCNN in FPGA,such as slow speed,high power consumption and serial acceleration,The thesis proposes a series of optimization methods.Based on the analysis of convolution circuit,the full parallel multiplication and addition tree module and efficient window cache module are applied to reduce the power consumption of acceleration.The block method of input image solves the problem of small on-chip storage space of FPGA.Combined with the advantages of network design and high level synthesis,the thesis proposes a new method to reduce the power consumption of acceleration,The thesis proposes a deep pipelining parallel architecture based on the convenience of Vivado HLS.Finally,the thesis completes the network simulation on Vivado HLS platform,and the experimental design proves the advantages of the network design and the effectiveness of the optimization method.