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Reconfigurable Architectures for Efficient Implementation of IIR Filters

Posted on:2017-09-12Degree:M.SType:Thesis
University:San Diego State UniversityCandidate:Jaikumar, GaneshFull Text:PDF
GTID:2468390011495409Subject:Electrical engineering
Abstract/Summary:
This thesis studies different methodologies for modeling infinite impulse response (IIR) filters and investigates efficient hardware architectures for the high throughput and compact implementation of IIR filters. The hardware implementation characteristics, such as performance of the architecture depends on the chosen filter structure. Rounding and quantization effects will be decreased by implementing IIR filters using cascaded second-order sections (SOS). Hardware implementation results of various structures run on a Xilinx Virtex-7 field-programmable gate array (FPGA) are obtained by synthesizing verilog descriptions. Performance and resource utilization for various designs are presented. This thesis also investigates the C-slow, clustered look-ahead, and scattered look-ahead pipelining methods and presents various architectures that facilitate efficient FPGA implementation. Scattered and clustered look-ahead pipelining result in high-speed pipelined realizations of recursive digital filters of logarithmic complexity with respect to the number of pipelined stages used. The designs are verified in customized fixed-point representation. We also present a technique to implement a high-order relatively low-bandwidth recursive low-pass filter without the brute-force requirement for extended precision coefficients and registers. We finally present K-stage multiplexed realization of the IIR filter for a compact implementation.
Keywords/Search Tags:IIR filters, Implementation, Efficient, Architectures
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