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Design And Implementation Of Co-prime Sampling System

Posted on:2021-01-20Degree:MasterType:Thesis
Country:ChinaCandidate:H Y YanFull Text:PDF
GTID:2428330623468602Subject:Instrumentation engineering
Abstract/Summary:PDF Full Text Request
Based on the traditional Shannon Nyquist sampling theorem,in order to obtain the complete information of the signal,it is necessary to sample the signal at a sampling rate of twice the highest frequency of the signal,which brings huge pressure to the hardware system,even in some cases,it can not be realized.In order to adapt to the growing demand,the sampling rate of the system proposed in this paper is far lower than that of Nyquist.Compared with the existing broadband converters such as multi coset sampling and modulation,it has a relatively simple system structure and can be realized with only one pair of samplers.The research content of this topic mainly includes the following parts:1)Model analysis of coprime sampling system: the system realizes high equivalent sampling rate with low actual sampling rate of two channels.Compared with traditional equivalent sampling system,it only needs a single acquisition,and compared with multi coset sampling system,its channel number is less.Combined with practical application,there is phase difference in the two channels,which needs to be measured and compensated in the observation matrix.Therefore,based on the synchronous coprime sampling system,the asynchronous coprime sampling system is further proposed.2)Acquisition circuit design: this part realizes data acquisition,the input signal is adjusted to the appropriate input range of the device through the signal conditioning part,and sent to the dual channel for sampling at the same time,and to ensure that the dual channel input is consistent,controlled and stored by FPGA.In addition,the dual channel sampling clock is provided by a pair of PLL chips,which is convenient to realize multiple sampling rate combinations.This part ensures the impedance matching of signal path,high signal-to-noise ratio of input signal and subsequent signal reconstruction.3)Design of storage and control circuit: this part includes data storage control,configuration of external phase-locked loop and reference clock input,implementation of time to digital converter in FPGA,measurement of start time difference between two channels and communication between FPGA and arm.Data storage and time difference measurement are controlled by FPGA at the same time to ensure correspondence.The dual channel start time difference is used to construct the compressed sensing measurement matrix,and its resolution directly determines the accuracy of waveform reconstruction.Because of the short time difference,the direct measurement will cause large errors and require high frequency stable clock.The method of this paper uses the abundant buffer resources in FPGA to design a high frequency division rate and high precision time digital converter to obtain the time difference.4)System performance test: in practical application,the device difference of dual channel ADC will worsen signal reconstruction.In this part,the influence of offset error,gain error and phase error on signal reconstruction and the probability of successful recovery of the system are tested respectively.
Keywords/Search Tags:coprimg sampling, sub-Nyquist sampling, time-to-digital converter(TDC)
PDF Full Text Request
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