Design Of IP Core In Infrared Image Processing SoC And Chip Testing

In order to improve the success rate of IP core development and shorten the development cycle, FPGA is often used to design and verify the IP core during the development of So C. In order to know if the So C has normal function after it’s taped out and packaged, FPGA is often used to provide test stimulus and receive the test response of the So C board level test.This paper is based on “the design and test of So C for infrared image processing”. The IP of generating control signals & acquiring image was designed and ran successfully based on FPGA, it was synthesized using Design Compiler and taped out successfully. In order to display image scene, the VGA image displsy system which was made up of controllable VGA controller and display buffer was designed based on FPGA. In order to provide test stimulus and receive the test response using FPGA during the process of So C board test, the udisk read and write system was developed based on the USB controller ISP1362. The hierarchical structure of Nios II firmware was introduced, it realized the functions of ISP1362 driver,USB transaction,USB control transfers,USB bulk transfers, Fat Fs file system transplantation and so on. Finally, the So C was tested based on udisk read and write system, the test image was read from udisk and provided to So C via intermediate-results-input interface, the test response was received from So C via intermediate-results-output interface and written into udisk simultaneously.The two IP core designed in this paper was synthesized in SMIC 0.18 um CMOS process with area 0.552mm2, power dissipation of 14.6553 m W, 120 MHz clock frequency and taped out successfully. VGA can displays the image of 640*480@60Hz. The function of datapath of So C was tested in default condition and proved to be correct.