Research On Customized Architecture Technologies For Solving Large Sparse Linear Equations

Since large-scale sparse linear equations involves large matrix size and irregularity memory access,it becomes the bottleneck of the current scientific and engineering applications in computing.In general platform architecture,it is difficult to improve the utilization of memory bandwidth and balance computing tasks on each core.Faced with this dilemma,customized technical architecture becomes a method to solve the problems involved in large-scale sparse equations.Customized architecture technology,from the bottom of the computer structural level,is combined with calculation algorithm,memory access and communication features to design a specific architecture.Doing so can make a dedicated computer architecture which matching the algorithm in nature,reaching the goal of fewer hardware resources,faster execution,less power consumption.The work should be carried out from two directions.First,it requires thoroughly study in the characteristics of the algorithm,or even to change the algorithm to improve its parallelism,memory access performance and so on if necessary.Second,you need to know basic computer architecture technology,research current computer computation,memory accessing and communication and other aspects of applications and performance.After an in-depth analysis of the main problems and solutions faced for numerical computation and cryptology,this paper focuses on solving large-scale sparse linear equations and hardware acceleration.Algorithms mainly involved in this research are key steps in the Cholesky algorithm and Wiedemann algorithm.For each algorithm,this paper analyzes its characteristic deeply,selects and improves the algorithm performance.Besides,it establishes a performance model for the implementation of the algorithm in order to find where the bottleneck of the algorithm lies.Then,it puts forward an optimization and customized system for the special algorithm structure.At last,it implements the hardware sheme and evaluates its performance on FPGA.