The Reliability Prediction Of Digital Phase-locked Loop Circuit

As the semiconductor processing technology enter the deep submicron era, integrated circuit develops towards highly integrated and the process sizes of device become smaller. It can bring the reliability problems of circuits. The performance of circuit will be affected when it subjected to the failure mechanism. With the affected time becomes longer, the aging of circuit will increase, even it can cause function error and system failure. In some high reliability requirements areas, such as aerospace, reliability even becomes the dominant factor in the whole system.For the digital phase-locked loop circuit can produce high-performance clock signals, it often applied to aerospace equipment, so its reliability is important. Digital phase-locked loop circuit in this paper includes four modules: time to digital converter, a digital filter, a numerically controlled oscillator and a frequ ency divider. The time to digital converter uses delay-chain structure, digital filter uses threeorder low-pass FIR filter, oscillator uses cross-coupled LC oscillator and the frequency divider can achieve three frequency division. The frequency range of the phase-lock loop in this paper is 15-40 MHz and the lock time is about 1.2μs.In this paper, it applies the device-level failure mechanism model to the circuit analysis and get the reliability prediction model of the digital phase-locked loop. The failure mechanism includes hot-carrier effects, negative bias temperature instability and radiation. The reliability prediction model of digital phase-locked loop circuit is about its delay time. Under three different failure mechanisms, the prediction value and simulation value of digital phase-locked loop circuit is approximately equal, which verify the correctness of the prediction model. At the same time, the results show that under one failure mechanism the delay time of digital phase-locked loop is more than four years when it increases 10%, under two the time decrease and under three failure mechanism it reduced to one year. The results indicate that with more failure mechanism in action on the circuit, the circuit becomes more serious and worse reliability.At the end of this paper, it executes the reliability test. By building the hardware experiment platform, it tests the reliability of the circuit and the results of test signal output through the data transmission module. Experiments show that, when the digital phase-locked loop reaches the lock state, its delay increases and reliability becomes worse with the action time of failure mechanism become longer.