Reconfigurable Component Modeling And Verification For Complex Digital Logic Systems

Digital logic systems are the important parts of modern embedded systems.With the growing application requirements, the digital logic systems becomemore and more complex. In the design process of complex digital logic systems,efficient modeling and verification methods are useful for divisional design andspecialized production, and those methods can ensure the success rate ofsystem design, shorten the design cycle, save production and design costs.Therefore, this thesis studies the reconfigurable component modeling andverification method of complex digital logic systems such as a digital appliancemicro-controller.The main contributions of this work are listed as follows.1. The reconfigurable component modeling and XML description methodsare proposed. In this method, logic mapping tables and finite state machines arerespectively used to model combinational logic components and sequentiallogic components, and the structural modeling method is used to modelingcompound logic components. All those components can be described in thecorresponding XML tabular specifications. This method provides a higherabstraction level strategy for the modeling of complex digital logic systems.2. A hierarchical component verification process is designed. Theeffectiveness verification, prototype function simulation verification, HDLverification and FPGA in-circuit verification are used to verify the systemmodel layer by layer. Those verification methods track the design process,verify the model effectiveness, so as to ensure that the model can truly reflectthe designer’s modeling intention, and detect some design errors which maybelead to modeling failures earlier. This method provides a higher designefficiency way for the verification of complex digital logic systems.3. A component modeling and verification platform called XModel is built.It provides the editing function of digital logic component modeling files, andsupports the effectiveness verification and prototype function simulation ofdigital logic components. It can also synthesize XML descriptions into VerilogHDL descriptions, so as to do further functional and timing simulation withexisted EDA tools. Finally the FPGA in-circuit verification can be completed.A digital appliance micro-controller is designed to verify the proposedmethods. Component modeling method is used to model this micro-controller,which is described in XML and verified in XModel.