The industrial Ethernet applicated in industrial control field has high speed,real-time and big capacity. Two of the most important performances of the industrialEthernet are real-time performance and determinacy. The former means that a systemmust be able to react to event in a limited amount of time, and the latter means that thebehavior of a system must be predictable under certain condition. There are two kindsof real-time performance, soft real-time and hard real-time. The difference betweenthem is that hard real-time means a limited amount of time which is unchangeable andunallowed to exceed. In real-time Ethernet field, Ethernet POWERLINK has manyadvantages such as high real-time performance, high determinacy, easy implementationat a low cost, great development potential and so on.The data processing rate and the speed of state machines should be accelerated toimprove the real-time performance of POWERLINK communication. Digital circuitshave the advantage of parallel processing so that data processing rate can be enhancedgreatly and the state machine implemented by hardware is faster than that implementedby software.According to Ethernet POWERLINK communication protocol and Ccode of the POWERLINK protocol stack, a series of circuits are designed in this paperwith Verilog HDL to implement functions of the protocol stack except for theapplication layer. First, a dual-port RAM is used as an interface for data exchangingwith application CPU. Second, a RMII interface is used to connect PHY chip. A fewdigital circuits are designed between the two interfaces above to implement functions ofthe NMT state machine and the DLL state machine. Then, an Ethernet controllermodule(MAC) designed with VHDL is added to the circuits to form a hardwareimplementation of the POWERLINK communication protocol,and the hardwareimplementation will have a higher hard real-time performance in theory. Finally, thesimulation software Modelsim SE is used to verify functions of a few modules. There are three aspects of work in this paper. Firstly,an user interface isimplemented by an DPRAM. Secondly,the state machines which are originallyimplemented by C code are now be implemented by Verilog by means of defining aseries of states. Thirdly, NMT functions and relevant state machines are implemented bydigital circuits to optimize real-time performance. All these work lay the foundation fordeveloping this implementation into an ASIC. |