Research And Implementation Of Mine Power Line Carrier Communication System Based On FPGA And OFDM

At present, underground coal mine’s communications network has been extended to gate road. But due to the harsh environment of integrated coal face, it is difficulty to communicate between the shearer and the gate road under the mine for a long time. There is important significance to achieve effective data exchange between the shearer and the gate road for the realization of mechanized mining automation, as well as high yield and efficient mining technology. Meanwhile, the OFDM technology fused with the channel coded has gradually become the third generation of PLC (Power Line Carrier Communication) core technology, and has been widely used to street lighting control system, communication under the mine and other fields. Therefore it has very broad application prospects.In this paper, a power line carrier communication data transmission system is designed based on the devices of FPGA and dsPIC33F family, which is used by the latest release of G3-PLC narrowband power line carrier communication protocol, channel coding modulation OFMD techniques and CAN bus technology. And it is used for bidirectional data transmission between the shearer and the monitoring center of the gate road on the integrated coal mining working face.In the hardware design of the system, Altera’s Cyclone Ⅲ family EP3C80F780C8N chip is mainly used as the baseband encoding and decoding core of G3-PLC protocol. Microchip’s dsPIC33FJ64GP706A chip is used as the main processor of CAN bus network. At the same time, the implementation principle, process of part of systems hardware modules are analyzed and described in detail. The DAC output drive strength and peripheral circuits, differential current to single-ended voltage circuit, the active low-pass filter circuit of 6-order Sallen-Key structure, single-ended signal to differential signal circuits, ADC driver and the front-end interface circuit, dynamic adjustment range of up to 80dB (-25dB-55dB) of AGC circuit, CAN bus interface circuit isolation, high voltage coupling circuit are mainly included in the hardware circuit modules. Meanwhile, the power of "soft start" control circuit is given in Appendix.In the design of software, first of all, frame synchronization preamble using Zadoff-Chu sequence is redesigned and simulated in the MATLAB platform. Meanwhile, the frame synchronization preamble and G3-PLC carrier protocol is also simulated and verified by MATLAB. And then, the C language is used to complete the CAN bus baud rate adaptive algorithm programming and receiving data, forward master programming based on dsPIC33FJ64GP706A controller by MPLAB IDE 8.90 Integrated Development Environment, XC16 C language compiler. Meanwhile, the adaptive detection time is tested. Finally, the Verilog language is used to complete baseband coding and decoding algorithm of G3-PLC protocol based on Coded-OFDM in Altera’s Quartus II 9.0 platform. The implementation process of baseband coding and decoding module mainly including the scrambling, descrambling, frame preamble output, add the cyclic prefix and add window, frames combined output, IFFT/FFT interface processing, coarse synchronization algorithm based on delay autocorrelation, synchronization algorithm based on fine local cross-correlation, DQPSK/DBPSK demapping are analyzed and explained in detail. Meanwhile, all of the above modules are simulated in the Modelsim SE 10.1c simulation platform.Finally, two sets of system hardware platform are built, and VS2008 software is used to design a PC test software in this paper. And the simulated docking one-way communication of the whole system is tested, which includes frame error rate of the system, frame loss rate, the cumulative error frame rate and so on. The results show that the peak to peaks value of the system no-load emission reaches 19.8V, CAN bus baud rate adaptive detection is correct, the whole communication link is normal, codec is correct; frame error rate, frame loss rate and frame error rate are zero. The whole system reaches the initial system prototype design effect.