Design And Simulation Of LXI-B Digital Oscilloscope Based On FPGA

Following the popularity of Ethernet in the electronic equipment, instrument busand the automatic testing systems based on Ethernet have gradually become a trend.LXI league proposes a new bus (LXI bus) from the original VXI bus specificationand technology. Since the originally version of LXI was born in2005, it belongs tothe young one in numerous bus technologies, so LXI equipments and otherequipments such as GPIB, PXI, VXI bus technology have existed in the marketsimultaneously for a period of time. But LXI based Ethernet can undertake large datatransmission over a long distance, and it is not dependent on expensive parts such asdisplay panels and chassis. Excellent magnetic properties and compatibility are alsothe characteristic of LXI. As a result, more and more measurement equipmentmanufacturers and scientific research units engaged in the production anddevelopment of LXI instruments. Based on the above trend, this paper proposes aresearch of B class LXI digital oscilloscope.First of all, the design of the MAC controller was realized using Veriloglanguage, which realizes the normal communication of Ethernet protocol in MII anddata link layer. The result of Modelsim simulation proves the correctness of thetiming and function. This paper built the SOPC architecture for TCP/IP and UDPprotocol at the basis of MAC layer, which implemented the function of TCP/IP andUDP protocol in the Ethernet protocol, which were verified by the display of PC anddevelopment board.Then, the design of multi-port SDRAM controller is given, which main includesthe state machine design and detailed interface design. Because the SDRAM has ahigh frequency, so the timing constraint is also proposed. The results of Modelsimsimulation verify the reliability of its function. After the completion of Ethernettransmission and storage design, the principle diagram of AD reasonable scanningcircuit design, interface design and timing function analysis are given. Thecombination of the three designs can ensure the stability of the AD circuit running.The results of the FPGA development board verify the correctness of the design. Finally, the delay time can be calculated by master-slave clock algorithm andthe network delay algorithm. So the state machine and Verilog code are simple andfeasible by the design of timestamp in the hardware circuit. Surface line and IVIdriver are designed by using the Labwindows software of NI Company. The runningresults show that the sine wave images verify the correctness of the platformselection and design.