Optimal Design Of CMOS OpAmp Based On Pareto Multi-objectives Genetic Algorithm

With the continuous development of integrated circuits，the increase of designcomplexity and demand of design cycle time reduction due to highly competitivemarket，IC design can only be managed by the use of powerful computer aided designtools. Regarding the design methodology for sizing analog integrated circuits，atransition has emerged from a "pencil and paper" approach，through a simulation-basedmanual tuning method toward an optimization-based approach.Analog design problem is essentially a multi-objective optimization problem that atradeoff exists between two or more competing objectives. Historically，this problemwas solved by combining all objectives into a single cost function. Typically，this costfunction consisted of a penalty portion and a true objective portion，all combined withweighting coefficients. The value of this global cost function was then minimized. Themain drawback of this method is that as a result of the conflict and non-comparabilitybetween different objectives，it is very hard to establish a real optimum criterion. Fordifferent objective functions or weighting coefficients，the optimization results are alsodifferent. These shortcomings hinder the practical application of the traditional circuitoptimization methods.Recently，the evolutionary based multi-objective optimization technique hasreceived attention in this field. As the real multi-objective algorithms，they trackmultiple design objectives concurrently and are capable of exploring the completedesign space boundary. The result of such algorithm is the so-called Pareto optimal frontin the design objective or performance space. Once the Pareto optimal front is obtained，the designer can select the optimal tradeoff from all the performance considered. Henceit overcomes the drawbacks of the single-objective optimization methods and is hopedto be an enabling design automation tool for analog IC design. Currently the dominantapproach to find the Pareto front is through multi-objective genetic optimization. Thegenetic algorithm is usually time-consuming. Besides，as in the case of the existingapproaches for circuit sizing，a circuit simulator is embedded in the optimizing loop.As a result，large amount of computations are required in order to find the Pareto frontof a circuit design problem.This paper presents an improved method based on the Non-dominated SortingGenetic Algorithm II (NSGA-II) to find the Pareto-optimal front for CMOS opamp circuits. The method is a two-stage algorithm which combines simulation-basedoptimization with analytical equations-based optimization. The first stage carries out theoptimization based on the approximate，analytical equations which derived from thefirst-order analysis of the circuit to be designed. This process is fast since all the circuitperformances and design constraints are calculated by analytical equations. But theresulted Pareto front is not accurate，only a rough approximation of the real solution.Next we use this approximate front as part of the initial population and continue themulti-objective genetic optimizing with a circuit simulator embedded for the evaluationof the design objective and constraints. The true Pareto front will be found when thealgorithm terminates. The time so consumed is reduced significantly. The method isillustrated with three examples of operational amplifier.