Design And Implementation Of Digital Image Noise Reduction And Enhanced Design

Complete digital video processing system generally includes the following aspects: the video information capture system; video storage; video information transmission; video processing; video information output and display. As the intermediate part between the capture system and the post-processing system, video pre-processing system aims at recovering the capture image as well as improving the quality of the image and provides the post-processing system a high-quality and reliable image. This paper mainly focuses on the image de-noising, image enhancement algorithms.Gauss noise and impulse noise are the two important factors which degrade the image quality. In this paper, de-noising algorithms based on image detail protection the weight coefficient of gauss filter and multi-decision algorithm are introduced to remove the two noise mentioned above separately. The weight coefficient of gauss filter is used to reduce the gauss noise with the consideration of gauss function and image brightness information, while the multi-decision algorithm replaces the noise pixel with the most suitable pixel of the filter window based on the multi-decision.As to image enhancement aspect, an adaptive enhancement algorithm based on dynamic scene estimation is proposed. Laplacian operators are used to sharp the image details. Then, several mapping curves are introduced to extend the dynamic range of the image gray-scale values, which improves the contrast of the image.Experimental results show that great effects are got when removing gauss noise and impulse noise as well as under different scenes by adopting this algorithm, what’s more, at the same time avoiding the distortion caused by the over enhancement and maintaining the original semantic of the image.The hardware design of all the algorithms proposed in this paper, only SRAM is used as the line buffer to guide the hardware design, which avoids using lots of external storage, such as SDRAM as frame buffer. It also meets the simplification and high efficiency requirements of the pre-processing system. The hardware implementation is completed on Altera FPGA.