Design And Implementation Of LDO Linear Power Chip With Large Current And High Stability

With the rapid development of integrated circuit (IC), several kinds of power chip are occupying such a flourishing market. Whether personal advanced computers or high performance microprocessors have high-efficiency and intelligent power management, directly impacts the performance of whole electronic system. This paper designs a low dropout (LDO) voltage linear power chip as one kind of power management schemes, which can provide a flexible and reliable power management for various electronic products, especially for portable equipments with battery power supply.For LDO chip, large current and high stability are developmental trends of power field, however, stability decreases as current increases, so it is a formidable challenge to design a LDO chip with large current and high stability simultaneously. This paper presents a LDO linear power chip with large current and high stability in 0.18um CMOS process. The post-layout simulation shows that it works well and meets practical requirements and has already been taped out.In this design, the LDO chip generates 1.8V output voltage and provides 1A load driving capability, much stronger than conventional designs. The twice compensation technique presented overcomes the conflict between large current and high stability, which greatly improves system stability and bandwidth. By employing low dropout PMOS adjusting transistor and U pattern layout design methodology, the large current and over heat problem have been solved. High performance bandgap voltage reference is also designed by introducing temperature compensation and negative feedback techniques, which has low temperature coefficient 7.9ppm/℃(0~100℃)and good power regulation capability. Moreover, off-chip delicate adjustment improves output voltage accuracy. The bandgap voltage reference has already been taped out as an independent IP.