Reserch On Base Band System Of "Bei Dou" Navigation Receiver

With the rapid development of EDA (Electronics Design Automation) technology, large-scale programmable logic chip CPLD/FPGA came into being. with the characters of designed with HDL(Hardware Description Language)and supporting IAP(In Application Programming) and ISP(In System Programming). It is used in wide range of field, especially in the Development of suitable system, but lack the ability to logic control. With high performance, low power consumption and cost, ARM has become the first chance of embedded products from mobile communication to portable equipment. The system constructed by FPGA plus ARM is complement, and now is more and more popular.This thesis is application of object "Bei Dou" base-band receiver system, most traditional digital receiver use sophisticate FPGA(intron NIOS) as its core, but sophisticate FPGA is expensive and NIOS is astaticism when working. This thesis give a new system configuration which designed by AD plus FPGA plus ARM, it replaced NIOS as ARM, and embed real-time operate systemμC/OS-II to ARM. Now ARM controls the whole system and executes part of tasks of data processing, minify the cost effectively and increase stability.The first chaper of this item put forward the research content of this thesis, exhausts meaning of the subject, present condition of embedded system and organize construct of the item. Chaper II investigates the programmed logic device FPGA in depth, including the design flow and configurative mode of FPGA, and gives a method of parallel loading FPGA with FLASH. Chaper III is the hardware design of this system. Firstly it bring up design meaning of the gross hardware structural, in accordance with FPGA and ARM building system, high-speed signal acquisition front-end for the AD, and increate FLASH and SRAM as a memory expansion, attach IC card on FPGA for "Beidou" data encryption; for the system to work, also design the power supply system, the clock and reset modules, and gives the schematic and PCB. Chaper IV is software design of the item. ARM is designed to guide Bootloader procedures, and have successfullyμC/OS- II operating system ported to the ARM. In FPGA logic for the development, designs the interface with the ARM; external display to the FPGA and design the software. Chaper V is smart card reaserch. ARM is used as smart card reader, and could visit smart cards in accordance with card agreement ISO7816-3. Chaper VI gives succinct statement and vista to the whole thesis. The author lodges own opinion about the trend of receive device of "Beidou".