Research Of A High Efficiency Current PWM Step-up Converter

With continuous development of automotive electronics, communication electronics, consumer electronics, power management chips play an indispensable role in the modern electronic equipments, especially in the portable battery-powered devices.In this thesis, with the help of commercial software package Hspice, a current mode PWM step-up Power management chip based on CMOS technology has been designed. As the key jobs of this paper, all of the chips producing flow have been finished, such as circuit design, layout simulation and chip produce. According to the laboratory test, results prove the validity of the sample.Firstly, the thesis analyzes the actual state and the development trend of the Switching Power Supply. Based on Switching Power Supply Control System the current mode PWM step-up converter is bring up to design. The main design targets include input ranges from 3V to 5V, stability output voltage 5V, operating frequency 170KHz, bandgap reference 1.23V, high classical efficiency more than 90 percent and small output ripple coefficient less than 1 percent.Secondly, the basic configuration of the chip is introduced, which includes amplifiers, bandgap reference, comparator, controller and driver, slope compensation, bias, as well as oscillator circuit. According to the simulation results by Hspice, chip design meets the requirements. Furthermore, this converter has been simulated functionally in various conditions, which results show perfect effect. The high classical efficiency is as high as 92.33 percent and output ripple is less than 0.05 percent.Thirdly, the basic rules of layout design are introduced in this thesis. For the purpose of reducing the mismatch circuit, the "multiple fingers" technology and the "common-centroid" technology has been used in this thesis to place the modules carefully; the influence of big power device and the capacitance on the sensitive circuits are reduced by separating them. After the whole layout design completed, the DRC and LVS verification are achieved.In this thesis the chip uses 0.5μm, N-well DPTM standard CMOS process to design. The testing results show that the performance of the current mode PWM step-up power management chip reaches the design requirements.