Research And Circuit Design Of Ultra-high Speed And Low Power Moving Accumulative Sign Filter

With the rise of mobile applications,chip application terminals are developing to the edge,and low power design of chip is becoming more and more important.Digital down-sampling filter circuit,as a key module to realize the conversion of high-frequency signals to low-frequency signals,has important research significance on how to break through the speed bottleneck and reduce power consumption.In order to solve this key problem,filtering algorithm,architecture implementation,circuit design and layout optimization are studied in this dissertation,and the ultra-high speed and low power consumption digital down-sampling filter circuit is realized.The main research results are as follows:(1)In order to solve the problem of insufficient processing speed of existing down-sampling filter circuit,the theory of down-sampling filter is innovated in this dissertation,and the moving accumulative sign filter algorithm is proposed.Sign operation is used in this algorithm instead of multiplication and division operation when only the polarity of the signal needs to be judged but no specific value needs to be output,which reduces the computational complexity.At the same time,the step length is the same as the extraction rate,so that the amount of data decreases according to the extraction rate.The simultaneous reduction of computational complexity and data volume enables the down-sampling filter algorithm to extract key information quickly.The transfer function of the moving accumulative sign filter is derived and the amplitude-frequency response is analyzed in this dissertation,which proves that the moving accumulative sign filter has the same level suppression ratio as the cascade integrator comb filter,and the filtering effect of the moving accumulative sign filter varies with the input data between the cascade integrator comb filter and the moving average filter.(2)To solve the problem of complex structure and large power consumption of existing down-sampling filter circuit,the moving accumulative sign filter based on pipeline voting architecture is proposed in this dissertation,and the pipeline series optional down-sampling circuits for binary and ternary signals are designed,the time-division multiplexing of circuit and hierarchical data processing are realized.Compared with the traditional down-sampling filter circuit using adder and multiplier,only D flip-flop and basic logic gate are used to realize the calculation effect of data accumulation and sign taking.The circuit of the moving accumulative sign filter is realized on FPGA.Compared with the cascade integrator comb filter,the logic unit is reduced by 86%and the power consumption is reduced by 88%under the same conditions.Compared with the half-band filter,the logic unit is reduced by 90%and the power consumption is reduced by 28%under the same conditions.(3)Aiming at the high speed and low power processing requirements of binary and ternary feature maps in lightweight convolutional neural networks,the polar-pooling algorithm based on moving accumulative sign filter is proposed in this dissertation.The algorithm only takes the sign of the sum of binary or ternary data,so it is named polar-pooling.Compared with the conditional operation of max-pooling and the division operation of average-pooling,the logical operation of polar-pooling has lower time and space complexity.The experiment of binary image processing proves that the processing speed of polar-pooling is 52%and 54%faster than that of max-pooling and average-pooling with the same processing effect.(4)In order to meet the requirement of clock data recovery circuit for high speed and low power majority voter,a second order serial majority voter is designed based on moving accumulative sign filter,and the circuit is optimized by low power design.The majority voter realized by two-stage voting without using multiplexer and counter,only uses the basic logic gates and D flip-flop,which simplifies the addition operation and sign operation to logic operation,eliminates the redundant output state of voting,reduces the flip of level,and the design of high-precision single-phase clock D flip-flop further reduces the power consumption of the circuit.The function and power consumption of the majority voter circuit are simulated in this dissertation,through the analysis of critical path,the maximum working frequency reaches 16 GHz by adding buffer to adjust timing reasonably.Compared with FPGA implementation,the optimized customized circuit can double the data processing rate,reduce the logic unit by 64%and the power consumption by 99%.(5)The majority voter designed in this dissertation based on the second order moving accumulative sign filter can realize the serial voting function of four consecutive decision signals,using 40 nm CMOS process design,the total area of the majority voter is only218.44μm~2,power consumption is only 0.55 m W at 10 GHz clock frequency.Compared with the existing majority voter,the area is reduced by 77%and the power consumption is reduced by 86%,which has great advantages.According to the test results of the chip,the whole design process achieves the design intention of low power consumption well.The proposed circuit has been applied to the receiver of ultra-high speed serial interconnection chip,the area and power consumption of the chip are reduced while maintaining the high-speed data processing capability.The down-sampling filter circuit proposed in this dissertation based on moving accumulative sign filter is especially suitable for edge and mobile chips with high speed and low power consumption,and has a wide range of application value.In addition,the model of moving accumulative sign filter can also be used in other digital signal processing scenarios,and can provide a method for high-speed and low-power optimization of circuits.