Deep level transient spectroscopy characterization of semiconductors

Deep Level Transient Spectroscopy (DLTS) is employed as a major tool in exploring deep levels in semiconductor materials. A computer controlled system was built to perform the measurements. The setup can detect defect densities down to 1/2000 of the carrier concentration at a standard temperature scan rate.; The concept of traps and generation centers in a depletion region is discussed, and the errors resulting from treating generation centers as traps in conventional DLTS derivation processes are demonstrated. Furthermore, an improved scheme is proposed to distinguish between these two kinds of deep levels and to deduce accurate defect parameters. The new scheme requires no other measurements besides DLTS. Applications of this proposed procedure on CdTe and GaAs semiconductors have proven EL2 in GaAs is an electron trap and V{dollar}sb{lcub}rm Te{rcub}{dollar} in CdTe is a doubly charged donor.; Native defects in organometallic vapor phase epitaxial (OMVPE) CdTe and GaAs have been investigated. For CdTe, the dependence of deep level concentrations on stoichiometry is characterized, and three major levels originating from native defects are identified. Among them, the tellurium vacancy is reported for the first time in DLTS characterizations. In GaAs, the growth condition dependence of EL2 is studied. The results suggest that this level is incorporated through more than one mechanism.; Ion irradiation induced defects in Si is another category of deep levels which is studied. Low energy (0-5 keV) ions is shown to create damage at positions well beyond their projection ranges. They are believed to be caused by diffusion of surface damages. High energy ion irradiation is investigated in the fabrication of shallow p{dollar}sp+{dollar}n junction diodes. Si preimplantations used in the process generate end-of-range defects in the lowly doped n-region and amorphous/crystalline interface damage. In both cases of low energy and high energy ion irradiations, the adverse effects of deep levels on device performance are discussed.