Testing platform implementation and system integration for an active /passive imager system including readout circuit desig

Designing readout schemes that were able to handle arrays with larger numbers of smaller pixels without losing information led to alternative options that would require neither too many capacitors nor too fast multiplexing speeds. A novel alternative readout scheme was tested and good results were achieved. These results proved that the scheme was able to read the data from the photodetectors and convert it to voltage using less capacitors for the same resolution, therefore, reducing size. After proving the principle, a big variety of possibilities that would improve this first approach in terms of noise, size, power and RF filtering appeared. Those were implemented in a 0.35-mum CMOS test chip to evaluate their functioning. It was indispensable to design a full testing platform to verify proper functionality and compare the different versions of the readout cells implemented. The platform includes from the code and control signal generation, to the output signal reading, including input signal emulation, printed circuit board design, testing and data acquisition.