Study On High Performance And Low Power MoS₂ Transistors

Since the invention of the semiconductor transistor,the scaling of the silicon-based field effect transistors has been continuously reduced,resulting in a tremendous increase in the speed and integration of chips.Silicon-based device technology is facing more and more challenges after the 90nm technology node.The use of new materials and new processes ensures that the devices can continue to meet their ever-decreasing size requirements in the past decade or so.The semiconductor industry guided by Moore's Law has entered the sub-10nm technology node.According to the sub-7nm complementary metal-oxide-semiconductor?CMOS?technology provided by The International Technology Roadmap for Semiconductors?ITRS?,the new channel materials in the post-silicon era is is an important choice to extend Moore's Law.Theoretical calculations show that thinning the channel thickness is the basis for continued reduction in device size.Based on the quantum confinement effect of materials,it is difficult for conventional three-dimensional materials to reduce the thickness to sub-5 nm.The ultra-thin body thickness of the two-dimensional semiconductor materials with sub-lnm intrinsic thickness show great potential in future device applications.Transition-metal dichalcogenides?TMDCs?represented by layered molybdenum disulfide?MoS₂?are one of the most important two-dimensional semiconductor materials.The ultra-thin body thickness,appropriate bandgap,and considerable room-temperature carrier mobility make it extremely useful for future electronics and optoelectronic devices.However,the current MoS₂-based electronic devices have many problems,such as unclear transport mechanism,low mobility,high extrinsic scattering,and so on.At the same time,due to the limitation of device technology,the currently reported MoS₂ devices also have problems of excessive driving voltage and large power consumption.The existence of numerous problems has severely restricted the application of this material.In response to the problems in performance and power consumption of the devices,we carried out corresponding research work and systematically analyzed the carrier transport mechanism of the MoS₂ devices.Based on the theoretical analysis,combined with the previous study of material defects,we conducted a systematic interface optimization to achieve the highest carrier mobility of monolayer MoS₂ transistors at room temperature.At the same time,a negative capacitance transistor incorporating a new operating mechanism achieved a sub-60mV/dec that exceeded the room temperature.The main research contents as follows:By systematically analyzing the scattering mechanism of carrier transport in MoS₂,it is concluded that carrier scattering mainly includes principal aspects such as intrinsic phonon scattering,remote phonon scattering,Coulomb impurity scattering,and elastic scattering of defects.Also,carrier number in conduction band is subject to the trapping effect of localized states.Based on the above factors,we present a systematical device transport modelling,use it to fit and analyze most of the currently reported high-performance MoS₂ devices,extract and analyze micro-parameters,and combine experimental results to give technical methods for improving and optimizing the device performance.Based on the theoretical analysis and fitting parameters of the current experimental results,we find that low device performance is mainly due to Coulomb impurity scattering at the interface.Therefore,we are committed to reducing the interface Coulomb impurity and suppress Coulomb potential strength in order to achieve improved device performance.Using MPS-SAM to passivate the oxide interface and reduce the number of impurities,we achieved a high room temperature carrier mobility of monolayer MoS₂ up to 150cm²/Vs/Vs,by combining the screening effect of the high dielectric constant substrate and high carrier density on the Coulomb impurity.Tthrough analysis of its transport behavior,we found that its carrier transport has entered the phonon-dominated regime.In order to solve the problem of SS degradation induced by short-channel effect,we studied ferroelectric HfZrOx as a dielectric layer,and used AlOx as a capacitance matching layer to prepare a back-gate ferroelectric negative capacitance transistor.The negative capacitance effect leads sub-threshold slope below the theoretical limit of the conventional devices,demonstrating new application potential for future devices.Our careful characterization of the ALD deposited HZO ensures that the HZO layer is a uniform ferroelectric material,and its intrinsic negative capacitance behavior is characterized using a pulse test.Furthermore,we compared the performance parameters of MoS₂ PCFET and NCFET devices.We found that the NCFETs can reduce the SS while effectively increasing the absolute current and transconductance of the device,suppress the off current and gate current,and reduce the operating voltage.These characteristic make NCFETs can be real high-performance and low-power devices.Also,we investigated the effect of the thickness of the matching capacitor layer and HZO layer on device performance.It has been found that reducing AlOx thickness can effectively reduce SS and does not introduce severe hysteresis.When the capacitance of the matching layer is reduced to-2 nm,we combine theoretical analysis to calculate that the stable state without hysteresis in the MoS₂ NCFET needs to satisfy the intrinsic value of HZO thickness below 28.6 nm,which is verified by our experiments.We found that 20nm HZO and 2nm AlOx are the optimized device parameters of MoS₂ NCFETs.