Lifetime Improvement Of NAND Flash Memory Using Digital Signal Processing Techniques

With the aggressive technology scaling and the multi-level per cell(MLC) technique, high-capacity NAND Flash memory has been widely employed in the consumer electronics, personal and enterprise computers. As the basic unit of the NAND Flash memory, the floating-gate MOSFET suffers damage during the data storing. The damage is aggravated as the device scaling, and hence severely decreases the lifetime of the NAND Flash memories. The badly degradation of the lifetime is a key issue which restricts the further development of the application of the NAND Flash memories.This thesis focuses on the lifetime improvement for the scaled MLC NAND Flash memories by the digital signal processing techniques. According to characteristics of the data-dependent lifetime of the memory cell and the error quantity difference between the physical pages, this work proposes some digital signal processing techniques to reduce the damage to the NAND Flash, and enhance the error correction capability of the memory device. As a consequence, the lifetime of the NAND Flash memory is improved. The main contributions of the thesis are:1. In the aspect of memory cell damage decrement, this work proposes a quantity-unchanged intra-page lossless compression technique. The average damage to the memory cell will be reduced by filling the less damage data content into the spare space from the compression, and changing the physical addresses and positions. To demonstrate its effectiveness, the theoretical models for the cell damage and the lifetime of NAND Flash chip are established. According to the test results of the data-dependent lifetime from a 19 nm MLC NAND Flash chip and the computer simulation results, the proposed intra-page lossless compression improves the lifetime of the NAND Flash memory: for the real stored data with compression ratio of 0.64 and 0.39, the lifetime is increased by 47.8% and 119.1%, respectively.2. In order to avoid changing the physical address which influences the flash translation layer, this work further proposes a damage-aware coding technique based on the intra-page lossless compression method. By increasing the ratio of the desired bit content, the proposed coding algorithm increases the ratio of the less damage data pattern among the stored data, so that the average damage of the memory cell will be reduced. According to the test results from the 19 nm MLC NAND Flash chip and the computer simulations, for the stored data with the compression ratio of 0.67~0.4, the damage-aware coding can decrease the average damage of the memory cell by 39%~51%. The corresponding decoding algorithm as well as high-throughput circuit structures of the encoder and decoder are also presented.3. In the aspect of the error correction capability enhancement for the NAND Flash memory, according to the un-balanced error quantity between the pages within one MLC NAND Flash wordline, a partial concatenated error coding method is proposed to further protect the data in the page with the worst error rate. In the proposed coding technique, the spare space, which is used to store the check bits for the error control codes of both pages, is re-scheduled to enable the further protection for the data in the worst error rate page by the concatenated coding. Accordingly, the lifetime of the page with the worst error rate in each wordline can be improved, and hence the improvement of the NAND Flash chip. According to the test results from the 19 nm MLC NAND Flash memory for the un-balanced error quantity between pages and computer simulations, the proposed partial concatenated error coding method can improve about 20% for the lifetime of the NAND Flash memory without any extra resources.4. The research also focues on the implementation of the Low-Density Parity Check code, which is the most popular error correction code used in NAND Flash memories. An improved decoding algorithm is proposed to enhance the decoding throughput, and the circuit structure of a rate-compatible decoder with high decoding throughput is presented. The proposed decoder is synthesized by ASIC and implemented with FPGA. According to the synthesis results, the decoder can achieve 600MB/s throughput for all the supported code rates at the working clock frequency of 415 MHz.