Optimal Design Of Tunneling Transistors Based On Two-dimensional Group ? Monosulfide Compounds

The rapid development of modern information society and people's pursuit of high-quality life promote the development of integrated circuits towards high miniaturization and integration.However,the short channel effect makes it more and more difficult to improve the performance of traditional transistors in the process of miniaturization.Tunneling field effect transistor can solve the short channel effect of traditional transistor in theory,because it breaks through the limit of traditional transistor subthreshold swing(SS)of 60 m V/dec.However,the two requirements of low leakage current and high on state current is hardly achieved in a two-dimensional planar p-i-n tunneling transistor device simultaneously at the same time.It'sthe key of tunneling transistor design at this stage that increasing the on state current while maintaining the low leakage current.This paper designs and optimizes the tunneling transistor with ML GeSe,ML GeS and ML SnS as channel materials based on the first principle quantum transport theory by using quantum ATK software and bilayer structure as electrode.The device performances o including on state current,subthreshold swing and local density of states are calculated.Then the performance limit of the optimized tunneling transistor is studied and compared with other two-dimensional tunneling transistors.The main achievements are as follows:(1)The tunneling transistor with ML GeSe as channel material is designed and optimized.The performance of the optimized device is studied and the mechanism of improving the on state current of the device is analyzed from the aspects of local density of States and gate control ability.Finally,the optimized device is compared with other two-dimensional tunneling transistors.The I_on of the n-type GeSe NHet J-TFETs using BL GeSe as the source and the p-type GeS Het J-TFETs using GeSe/Ge Te vd WH as the drain are 2320 and 2387?A?m^-1 for high-performance(HP)application,respectively,which are 50%and 64%larger than I_on of the ML GeSe TFET,showing the advantage of imposing homojunction or heterojunction in a TFET configuration.Inspiringly,both the optimal n-type GeSe NHet J-TFETs using BL GeSe and p-type GeS Het J-TFETs using GeSe/Ge Te vd WH meet the requirement of the International Roadmap for Device and Systems(IRDS)HP device for the year2034 at a low V_dd of 0.5 V.(2)The tunneling transistor with ML GeS as channel material is designed and optimized.The performance of the optimized device is studied and the mechanism of improving the on state current of the device is analyzed from the aspects of local density of States and gate control ability.Finally,the optimized device is compared with other two-dimensional tunneling transistors.The optimal device architecture for both p and n-type GeS Het J-TFETs is using GeS/Ge Te vd WH as the drain and an apparent promotion of I_onby 170?310%compared with the ML GeS TFET is achieved.About 23-58%part is contributed from the vd WH electrode and the left42-77%is from the induced strain in the optimal GeS Het J-TFETs with GeS/Ge Te vd WH electrode.I_on(LP/HP)of 463/878?A?m^-1 of the optimal p-type 10-nm-L_gGeS Het J-TFETs meet 89/95%of the IRDS requirements for the year 2028.Specifically,the p-type 10-nm-L_g GeS Het J-TFETs possess the highest I_on(LP)and I_on(HP)when I_leak<10^-6?A?m^-1 compared with other 2D TFETs despite the material type and device architecture and own superior energy efficiency compared with 2D MOSFETs.(3)The tunneling transistor with ML SnS as channel material is designed and optimized.The performance of the optimized device is studied and the mechanism of improving the on state current of the device is analyzed from the aspects of local density of States and gate control ability.Finally,the optimized device is compared with other two-dimensional tunneling transistors.The I_on of the GeS Het J-TFETs is using SnS/SnSe vd WH and SnS/Ge Te vd WH as the drain electrodes are42?51%/43?49%of the 912/495?A?m^-1,the I_on of IRDS for HP and LP consumption devices,which is significantly improved compared with the ML SnS tunneling transistor.It is found that the performance of GeSe as channel tunneling transistors is the best in HP devices that the optimized configuration is more suitable for HP devices.The optimized ML GeS material as channel tunneling transistor has the best performance in LP devices,which the optimized configuration is more suitable for LP devices.The ML SnS optimization structure is less effective compared with the former two optimization methods,but it also achieves certain optimization purposes.It is found that using homojunction or heterojunction as source or drain can effectively improve the I_on of tunnel transistor devices and solve the problem of low I_on of planar tunnel transistors through the study of tunnel transistors with ML GeSe,GeS and SnS as channel materials in this paper.This result provides a theoretical reference and support for the performance optimization of tunneling transistors.