Flash Memory Test System Design And Implementation

With the vigorous development of the integrated circuit industry and the popularization of smart terminals,the market for memory chips continues to expand.Against this background,chips and related testing equipment are heavily dependent on foreign imports.The memory test system can perform a full range of functional and parameter tests on memory,and is widely used in design verification,manufacturing,finished product testing and other processes.Therefore,it is necessary to study memory test methods and test equipment.The main research contents of this thesis include:1.Research on flash fault mechanism and test graphics algorithm.As a kind of nonvolatile memory,the memory cell in FLASH can save the content that has been written in the case of power outages,and also supports erasing and reprogramming of the memory cell.The purpose of functional testing of FLASH is to detect possible functional failures in the process of design,manufacture and use.According to different fault causes,a variety of fault models can be abstracted and detected by different test pattern algorithms.2.The hardware design of FLASH memory test system.According to the test needs,this subject divides the overall test system into four parts: the main control CPU,backplane,power supply board,and functional test board.As the core part,the functional test board is responsible for the functions of test vector generation,processing,sending,and result comparison.When running the test,the test signal is transmitted to the test interface board through the cable,and finally connected to the chip pins.3.Generation and output of digital test patterns.The test pattern requires that a single vector be reorganized according to the preset timing edge information before being sent.At the same time,the return comparison point for the expected result is also determined by the edge information.Thesis compares the advantages and disadvantages of various code generation and output schemes,discusses the impact of different schemes on generation speed,resource overhead and cost,and selects an appropriate delay-based pattern generation method.4.Test graph generation and protocol conversion.The test system supports hardware to generate specified test graphics,or use the user-defined test graphics designed by testers to test the function of flash.The graph generation module is used to generate the currently selected test process and test graph,and the protocol conversion module converts the test graph that cannot be used directly into the test vector that follows the memory control protocol.Due to the use of hardware to generate test graphics,compared with the use of general automatic test equipment to test the memory,the test efficiency is greatly improved.This thesis has developed a FLASH memory test system based on distributed design,with Pin Parametric Measurement Unit(PPMU),and the ability to generate and test various test patterns for FLASH memory.It can be extended to form an ultra-large-scale memory test system to achieve "testing multiple chips at the same time",which greatly improves the test efficiency.The system can also be used as a digital test equipment to test common digital chips.Finally,a complete test including functional test,DC parameter test,and AC parameter test is carried out using this test system for the chip MT28FW02 GBBA,and the test results are analyzed.