Research On The Core Circuit Of CDR In High Speed SerDes

With the development of integrated circuit technology,the iteration and update of the process has become more and more frequent,the integration of processors has become higher and higher,and the ability to process data has become more and more powerful.However,due to the limitations of packaging technology,the growth rate of I/O pin is far below the level of technological development,and massive,high-bandwidth,and high-speed data transmission is facing severe challenges.With the increase of data rate,traditional parallel interface technology is facing more and more serious problems of multi-channel data coupling and crosstalk.SerDes technology emerged as the times require.It is a time division multiplexing,point-to-point high-speed serial transmission interface technology.Convert multiple channels of parallel data into one channel of high-speed serial data and transmit it through optical fiber and other media,and the receiving part restores it.The clock and data recovery circuit(CDR)is the core part of the SerDes receiver.It recovers the clock signal from the distorted data,and uses the clock signal to sample the received data signal to recover the data signal.This article uses TSMC 40nm CMOS technology to design a CDR with wide rate range.Through investigation and analysis of the research status of clock and data recovery circuits at home and abroad,several typical CDR system structures are analyzed,and the structure of the CDR system used in this article is finally determined.This article adopts a dual-loop structure without reference clock based on HS?BBPFD(Half Speed Bang-Bang Phase Frequency Detector).The half-rate structure reduces the difficulty of designing a broadband voltage-controlled oscillator;The dual-loop is introduced to compensate for the shortcomings of limited frequency capture range of phase detector,it increases the frequency capture range of the CDR.The phase detector adopts half-rate Bang-Bang structure,which meets the requirements for phase detection of high-rate pseudo-random data;The frequency detector adds an AND gate circuit to the half-rate Bang-Bang phase detector to realize frequency detection function.the frequency detection is integrated into the phase detector,which not only reduces the layout area,but also reduces the power consumption and cost.The charge pump circuit uses current replica technique to reduce current mismatch and variation within a wide output voltage range.The simulation results show that the structure has extremely low current mismatch and current change,and is not affected by process,voltage and temperature.The voltage-controlled oscillator uses a four-stage fully differential ring voltage-controlled oscillator,whichcombines coarse and fine adjustment.The coarse adjustment uses a load resistor array to select the frequency band.The fine adjustment controls the on-resistance of the MOS tube to achieve fine adjustment of the frequency.Introduce a programmable quadrature frequency divider to expand the frequency coverage of the voltage controlled oscillator and achieve data recovery in a wide range of rates.Finally,the TSMC 40nm CMOS process is used to complete the schematic and layout design of the entire CDR system,the layout area is 0.3936mm~2.The post-simulation results show that under the power supply voltage of 1.1V,the structure can recover data with an input rate range of 350Mbps-3Gbps,and has good jitter performance.When the input data rate is 3Gbps,the recovered clock jitter is 0.1186UI,the recovered data jitter is 0.1214UI,which meets the design index requirements.