Design And Implementation Of AES Hardware Accelerator

The information security has attracted more and more attention along with the development of digital age,so lots of encryption/decryption algorithms have been presented and applied in various relevant applications.In many application fields hardware implementation for these encryption/decryption algorithms is needed,and this dissertation just studies the hardware implementation of AES(Advanced Encryption Standard),a kind of effective encryption/decryption algorithm.The dissertation mainly designs the structure of AES hardware accelerator and completes the hardware implementation of its three component modules: bus interface module,AES control module and AES encryption and decryption core.The key point of the dissertation is how to design and optimize the AES encryption and decryption core.AES encryption and decryption algorithm requires multiple rounds of operation,and each operation round can be divided into four steps: Sub Bytes,Shiftrow,Mix Columns and Add Round Key.In the dissertation,the cyclic architecture is used to implement the AES encryption and decryption algorithm,in which the hardware logic for one operation round is reused for all operation rounds of the algorithm.In the architecture of the hardware logic for one round operation,32 bit width is adopted so that each operation round can be finished in four cycles to balance between area and performance.In the hardware implementation of Sub Bytes,the scheme of composite field is adopted so that its hardware overhead is reduced.In the hardware implementation of Mix Columns and Inv Mix Columns,the hardware logic of Mix Columns is reused with Inv Mix Columns.By adopting the above methods,the area and power consumption of the AES encryption and decryption core are effectively reduced.Meanwhile,in order to resist the side-channel attacks to AES,the mask protection technology is adopted in the design,which can hide the intermediate results of AES operation with mask.In order to resist the fault injection attacks to AES,the fault detection scheme based on parity check is adopted,so as to detect AES operation errors caused by external attacks in time.Furthermore,the AES hardware accelerator can also realize AES encryption and decryption function with three kind of key length such as 128 bit,192bit or 256 bit,and support several chaining modes such as ECB,CBC,CTR and the CMAC used in message authentication.Meanwhile,AHB Slave interface,DMA interface and interrupt function are added in the design,so that the AES hardware accelerator can be more easily integrated into a system chip.A simulation platform is built to verify the functional correctness of the design in the dissertation,and Synopsys DC is used to evaluate performance and area of the design.The verification and evaluation results show that the functions of AES hardware accelerator designed in this dissertation have been correctly realized,and the performance and area have been optimized.