| With the rapid development of the information society,cryptographic chips are used in many applications,such as bank cards,ID cards,or military or medical careers,which are closely related to people's lives.At present,a technology that uses side channel information of cryptographic chips to attack has emerged on a large scale.In particular,attacking using power consumption information poses a huge threat to the security of cryptographic chips.At present,the power consumption attack technology has developed to the high-level attack stage.The ordinary first-level protection is no longer sufficient to meet the security requirements of the cryptographic chip,and the high-level defense technology is often accompanied by a huge area overhead.In order to adapt to applications where cryptographic chip resources are limited,it is necessary to study an efficient anti-power attack defense technology.Based on the AES algorithm,this paper proposes an anti-power attack defense technology that takes into account high security and low performance overhead,and completes the design of the secure AES circuit based on this defense technology.Aiming at the problems of high design complexity and large area overhead of AES circuit,this paper studies the current implementation of the secure S-box,and on this basis,proposes a complex domain-based cyclic S-box mask(CDRSM)defense scheme.The defense scheme redesigned the cyclic S-box mask(RSM)scheme on the composite domain-based S-box,and adopted the cyclic mask to protect the input and output of the masked S-box.Through the selection and design of the mask,different mask protections are added to the newly introduced key intermediate values,which further improves the security of the mask S-box.This cyclic S-box mask defense scheme based on composite domains combines the advantages of low cost of S-box area implementation based on composite domains and high security of the cyclic S-box mask scheme,which makes the circuit area overhead of the mask S box is reduced,and the defense overhead is equivalent to the first-order mask.In terms of security,it can resist first-order and high-order power attacks.Based on the CDRSM defense scheme,the design of the full-mask AES circuit was completed.This paper proposes an in-round pipeline AES architecture.This structure performs hardware multiplexing on round transformations,so that only one round of transformation is needed to complete ten rounds of AES encryption and decryption functions.The four-stage pipeline design for the round transformations reduces the area overhead of the AES circuit and increases the throughput rate.Then,on the basis of this architecture,the design of pipeline structure,round conversion multiplexing,mask correction module,etc.is completed.Add mask protection to all intermediate values of the AES circuit,and use the cyclic mask scheme to add different mask protections to the key intermediate values in the round transformation to resist second-order attacks,which improves the security of the full-mask AES circuit.And only implement the CDRSM defense scheme for the first and last four round transformation,and the remaining intermediate rounds are protected by a single mask,which further reduces the area overhead.Compared with the general high-level defense scheme,the whole design has low random number overhead,greatly reduced circuit area overhead,and increased throughput,which can resist high-level power attacks.Based on SMIC0.13?m process library,the full-mask AES circuit based on the CDRSM defense scheme proposed in this paper is synthesized.The simulation result shows that the circuit area is 182806.74?m~2,is comparable to the area overhead of the first-order mask;the highest frequency is 192MHz.Finally,a power analysis attack platform was established using EDA tools and Matlab to verify the security of the full-mask AES circuit based on CDRSM defense proposed in this paper.It proved that under 8000 power consumption data,the platform cannot successfully attack the full-mask AES circuit. |
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