Research On Digital Image Scaling Algorithm And Its Hardware Design

In consumer electronics fields such as mobile phones and televisions,the image quality presented by terminal devices intuitively reflects the pros and cons of their performance.The scaling algorithm used in the image processing chip of these devices directly determines the image quality and resolution,so the research on scaling technology has a broad industry background.In these consumer areas,scaling chips must not only ensure the quality of the display effect,but also consider the rationality of the hardware implementation cost,so the research mainly focuses on the analysis and comparison of image scaling algorithms and their hardware design.This article first explores the principle of image scaling to obtain the ideal interpolation scaling function Sinc.However,the ideal Sinc interpolation is infinitely expanded in the spatial domain and is physically impossible to achieve.Therefore,different scaling algorithms use various methods to approximate and fit the Sinc amplitude-frequency characteristics to achieve the image.Zoom.Therefore,this article uses MATLAB to compare the amplitude-frequency characteristic curves of different scaling algorithms as the theoretical basis for algorithm comparison.At the same time,due to the strong subjective uncertainty in the evaluation of the image zoom display effect,this paper establishes a unified image quality evaluation system combining the subjective score DMOS with the objective score PSNR and MSE as the scientific indicator basis for the simulation experiment.Secondly,according to the specific functional indicators of the hardware design,after weighing the specific indicator requirements of the algorithm effect,the implementation complexity and the chip hardware resources,this paper proposes a four-point segmented quadratic interpolation scaling algorithm,and uses the Laplace sharp The transformation algorithm is used as an image post-processing module to supplement the high-frequency information of the image.Finally,the amplitude-frequency characteristics are obtained by MATLAB,and the horizontal simulation comparison experiment between the piecewise quadratic interpolation algorithm and the three classic scaling algorithms is designed.Based on the dual basis of theory and simulation experiment,it is concluded that the scaling effect of the four-point segmented quadratic interpolation scheme in this paper is second only to bicubic interpolation,but it is far superior to bicubic interpolation in terms of hardware resource usage and speed.According to the proposed four-point segmented quadratic interpolation scaling algorithm,this paper presents a horizontal and then vertical quadratic scaling kernel architecture,discusses the module functions,workflow and data flow of the entire scaling architecture,and starts from top to bottom.The key technical issues in the hardware structure of the key sub-modules are analyzed in detail.In the clock module,the specific calculation formulas for frame synchronization and asynchronous FIFO not overflow and not underflow are analyzed for timing constraints;in the line buffer module,for read and write data control,the read and write state machine is analyzed and the line update data accumulation is designed.The line?updata?Acc is used to control the buffered data;in the fixed-point error analysis of floatingpoint numbers,for the fixed-point strategy of interpolating the decimal offset and intermediate calculation data,a simulation comparison experiment of fixed-point numbers and floating-point numbers from 4bit to 11 bit is designed,according to the experimental data,Under the premise of ensuring that the data does not produce errors,the fixed-point solution that saves the hardware bit width resources is adopted.At the same time,because the traditional FIR interpolation filter needs to store a large number of filter coefficients at different zoom ratios,this paper proposes an optimization design of the interpolation filter based on the FARROW structure,so that when the zoom ratio changes within a fractional range not greater than 1,It only needs to change the fractional interpolation offset ? and the original filter coefficients do not need to be recalculated,which greatly saves the storage resources of filter coefficients.Finally,according to the principle of hardware functional verification,a verification platform is built,and Modelsim is used to perform functional simulation of each key function module,and at the same time,the output results are compared with the MATLAB algorithm model.According to the waveforms verified by simulation,coverage report analysis,MATLAB result comparison,DMOS,PSNR,MSE,and calculation of the number of hardware resource gates,the hardware design has completed the functional index requirements and the hardware cost is far better than the bicubic interpolation with the best scaling effect.