Timing Analysis And Optimization Design Of Digital Chip Based On 12nm Process

With the rapid development of the integrated circuit industry and semiconductor technology,while facing more and more opportunities,the digital chips design is also facing more and more problems.Timing is one of the most important performance indicators that need to be considered in the process of digital chip design,and the circuit can only achieve correct functions when it meets the correct timing relationship.Static timing analysis has its obvious advantages.According to specific EDA tools,process technology and digital chip design,selecting the appropriate timing analysis mode and effective timing optimization method is the primary task of back-end physical designers and timing analysis engineers.This thesis selects the BTSYS module for timing analysis and optimization design based on the back-end physical design process of a certain digital chip under the advanced 12 nm process technology.This thesis first introduces the basic principles and processes of STA,and further studies and analyzes the impact of on-chip variations on timing and the timing analysis principles.Secondly,combined with the various physical design stages of the backend design tool Innovus,the physical design of the module is carried out with the goal of timing optimization.At the same time,this thesis studies and analyzes the application implementation methods of OCV,AOCV and SOCV timing analysis modes,and completes the establishment of the timing analysis environment.And this thesis analyzes and compares the timing results from the worst negative slack,the total negative slack,number of timing violations,and timing analysis time to verify the impact of different timing analysis modes on the accuracy of timing analysis results and the design cycle,and summarizes the advantages and disadvantages of the three timing analysis modes.Finally,specific application scenarios of timing optimization strategies are proposed based on the timing ECO process of the tool Tweaker,such as “vt?swap,sizing,insert buffer,split load,bypass buffer,split cell,adjust clock tree” et al,and some automated scripts are completed.And this thesis analyzes various timing violations and proposes strategies to optimize and repair setup,hold,min pulse width,glitch,and DRV violations,so as to meet the requirements of timing sign-off.The timing analysis results after routing optimization in physical design show that WNS in the OCV mode increased by about 51.4% compared to the BC-WC mode,and TNS increased by about 61.3%.On-chip variations have a significant impact on the timing analysis results,making the timing analysis results more pessimistic.Compared with the OCV mode,WNS in the AOCV mode is optimized by about 29.7%,and TNS is optimized by about 44.8%,which eliminates the pessimism of OCV mode.The SOCV mode simulates the randomness of the variations.Compared with the AOCV mode,WNS is improved by about 20.2%,the TNS is improved by about 18.4%,and the timing analysis time is also saved by about 28.4%.The timing analysis results verify that the SOCV mode can accelerate the timing closure speed of the physical design stage,and it's a better timing analysis mode under the advanced12 nm process technology.At the timing ECO stage,this thesis proposes corresponding strategies and applicable scenarios for timing optimization,and meets timing closure requirements after optimizing and repairing various timing violations.Therefore,the work of this thesis can indeed show that the implementation of accurate and efficient timing analysis mode and timing optimization strategies can improve the accuracy of timing analysis results and speed up the design cycle under the advanced process technology.