PCB Optimization Design Based On SiC MOSFET

Silicon power semiconductor devices have experienced many generations of development in the past 60 years,and they are close to the theoretical limits in terms of blocking voltage,operating temperature,conduction and switching characteristics.The emergence of the third generation wide band gap semiconductor device(WBG)based on silicon carbide(Si C)and gallium nitride(Ga N)provides a good solution to break through this limitation and will become the development trend in the future.Among the WBG devices,SiC devices have higher operating voltage and power levels,so Si C has more advantages in the current high-voltage,high-temperature and high-power applications.However,the high-speed switching performance of WBG devices poses a unique challenge to the layout of power and drive circuits,and high-frequency switches will inevitably lead to higher di/dt and dv/dt,-induced voltage and current oscillations.In this thesis,the basic principle and key characteristics of the dynamic characterization of the device are introduced in detail,and the three main testing tools of DPT,oscilloscope,voltage probe and current probe,are briefly introduced and comparative experiments are carried out.Through the experimental results,the advantages and disadvantages of several test probes are obtained,and a double-pulse test platform is built to minimize the impact of external parameters on the test results.By using the vertical multi-loop layout to reduce the parasitic parameters of the PCB power loop and the drive circuit,the current flow is inserted into a conductor with opposite flow direction between the same conductors,which can increase the distance between the conductors with the same flow direction and decrease the distance between the conductors in the opposite direction,thus making the flux offset more obvious.Aiming at the phenomenon of device mistriggering caused by gate voltage oscillation when high frequency devices are turned off,this paper puts forward the PCB design instructions to optimize the mistriggered oscillations through Barkhausen criterion and related mathematical analysis.Through the Q3 D parasitic parameter extraction software,it is found that,compared with the existing methods,the parasitic inductance of the gate circuit is reduced by about 30%,and the parasitic inductance of the power level circuit is reduced by nearly 50%.The effectiveness of the method is verified by Pspice simulation software.Finally,through the double-pulse test platform,the comparison data of the new PCB layout and the vertical power loop layout under low voltage,high temperature and high pressure working environment are obtained.Through mathematical analysis,it is found that the switching time of the new layout is reduced by nearly 6%,the switching loss is reduced by nearly 8%,the overshoot of current and voltage is reduced,and the switching loss and turn-on and turn-off time of the device are reduced.It can provide theoretical guidance for the PCB layout of SiC devices.