Font Size: a A A

Design And Verification Of Anti-Radiation IO For SMIC18 Process

Posted on:2022-07-03Degree:MasterType:Thesis
Country:ChinaCandidate:N ZhangFull Text:PDF
GTID:2518306572463924Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
Since the development of integrated circuits,its application scenarios have become more and more extensive.More and more So C chips are used in aerospace systems.In the space radiation environment,the chips will be affected by various radiation effects.The input and output(IO)unit is the bridge that connects the internal and external circuits of the chip.In order to prevent the high-energy particles in the space from affecting the inside of the chip through the chip pins,the IO unit needs to be designed for radiation resistance.At the same time,the IO unit must also interact with the inside of the chip.The unit itself provides electrostatic protection.This article carries on the anti-radiation and anti-static design to the input and output unit,verify after the design work is completed,and use the unit in the chip design.This article is based on the SMIC0.18 ?m process,on the basis of the IO unit provided by the manufacturer,combined with anti-radiation reinforcement measures,the circuit and layout of the reinforcement design are carried out.The designed antiradiation IO unit types include ordinary input units,input units with pull-up and pulldown functions,input units with Schmitt triggers,output units with different drive capabilities,and power supply units.For the electrostatic discharge(ESD)protection of IO cells,gate-grounded NMOS(GGNMOS)devices and power clamp structures are used,GGNMOS devices are modeled using TCAD tools,mixed simulation based on the human body model,and the power clamp structure is redundant It is reinforced to realize electrostatic protection and increase the ability of anti-radiation.Then the layout is reinforced by adding a guard ring.On the one hand,the parasitic diode absorbs the charge generated by the total dose effect;on the other hand,the gain of the parasitic transistor is reduced to resist the impact of single event latch-up;and the number of through holes is increased and the increase The spacing between the MOS tubes reduces the influence of the parasitic parameters of the layout to resist the single event effect.Finally,the radiation resistance and ESD protection performance are analyzed,and the designed unit can effectively resist 40 Me V·cm2/mg high-energy particles and 2k V HBM ESD stress.In this thesis,the designed circuit and layout have been simulated and rule checked.After the inspection is passed,the timing information and physical information are extracted,and the radiation-resistant IO unit library files are sorted.The radiation-resistant standard unit library and the designed radiation-resistant IO unit are used.Completed the design of anti-radiation SRAM controller based on I2 C protocol.The semi-customized design method is adopted in the design stage,which can simplify the chip design process and shorten the cycle while ensuring the functions and the requirements of anti-radiation performance to the greatest extent.The chip layout after automatic placement and routing has passed the DRC and LVS inspections.The design has been delivered for tape-out,indicating that the designed library unit can be correctly used in the integrated circuit EDA design process,and the correctness of its function has been verified.
Keywords/Search Tags:Radiation resistance reinforcement, IO unit, Single event effect, Total dose effect, Electrostatic protection
PDF Full Text Request
Related items