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A High-reliability Deep Neural Network Accelerator With Hybrid Architecture

Posted on:2022-09-01Degree:MasterType:Thesis
Country:ChinaCandidate:Q L WangFull Text:PDF
GTID:2518306560980049Subject:Microelectronics and Solid State Electronics
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The huge success of deep learning has inspired the application of deep learning in many application fields.To achieve higher performance and energy efficiency,researchers are increasingly implementing Convolutional Neural Networks(CNN)models,on custom Deep Learning Accelerators(DLA).But the reliability of model execution depends largely on the underlying accelerator.At the same time,DLAs made with ever-shrinking semiconductor technology are more susceptible to manufacturing defects and more sensitive to operating conditions such as large temperature changes than ever before.Hardware failures on the conventional 2D computing array of the Deep Learning Accelerator(DLA)can result in serious loss of prediction accuracy.Previous work has raised the issue of adding homogeneous rows,columns,or diagonal processing units(PEs)to mitigate the failure of PEs,but each redundant PE can only be used for a limited area(such as rows and columns).This causes them to be unable to recover compute arrays when the number of failed PEs in any region exceeds the number of redundant PEs in that region.The mismatch problem is exacerbated when the fault injection rate increases and the fault distribution is uneven.To solve this problem,we propose a hybrid computing architecture(Hy CA)for faulttolerant DLA.With previous to PE homogenous redundancy row or column calculating added to the 2D array of existing work,it has a set of dot product processing unit(DPPU),DPPU can parallel computing each output characteristics,and won't delay the 2D array of computing,so we can all faults in the array output feature mapping to the PE on DPPU recount.When the computational capacity of the DPPU is greater than the computational requirements of the fault PE,the neural network execution can be resumed without any loss of performance or accuracy.According to our experiments,Hy CA shows significantly higher reliability,scalability,and performance,with less chip area loss,compared to traditional redundancy methods.In addition,by taking advantage of the flexible recalculation capability,Hy CA can also be used to scan the entire 2D computation array and effectively detect fault PE at run time.
Keywords/Search Tags:Hybrid Computing Architecture, Fault Tolerance, Fault Detection, Deep Learning Accelerator
PDF Full Text Request
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