Research On Power Simulation Method Applied To VLSI Reliability Sign-Off

With the development of emerging technologies such as 5G,AI,and the Internet of Things,there are higher requirements for the power and reliability of chip design;at the same time,due to the integrated circuit process technology to nano-scale,reliability of the chip facing severe challenges.It requires precise reliability sign-off for chip design.Reliability sign-off needs to consider many factors such as power consumption,power integrity,and thermal influence.Among them,power simulation is an extremely critical part: on the one hand,power is a key indicator in the reliability sign-off;on the other hand,power integrity simulation and thermal simulation depend on the results of power simulation.The accuracy of power simulation directly affects the accuracy of reliability sign-off results.However,there is still no standard solution in the field of power simulation.In practical application,we find that the existing solutions have the phenomenon of policy mismatch and inconsistent results.In addition,because the domestic semiconductor industry is facing foreign technology blockades,the industry urgently needs EDA solutions with independent intellectual property rights.In this context,this paper comprehensively analyzes the existing power simulation solutions,and proposes a power simulation method for VLSI reliability signoff,The main contents of this paper are as follows:1.Based on the research on the static analysis mode of mainstream power simulation solutions,this paper designs a static simulation method for gate-level physical design of steady-state power.Considering the application scenarios,the signal path characteristics of gate level design and the characteristics of nanoscale process library,we propose a path driven propagation method based on global toggle rate and static probability,and a gate level power calculation method based on toggle rate and static probability.The method can propagate global activity information to each basic unit of the circuit according to the circuit path relationship and unit logic function,and accurately calculate the steady-state power of the circuit based on the activity information of the basic unit.Finally,based on this method,we designed the software architecture,completed the code development,and simulated three chip designs under different processes.The minimum error of the total power is-0.82%.2.According to the research on the dynamic analysis mode of mainstream power simulation solutions,this paper designs a dynamic simulation method for gate level physical design instantaneous power consumption.Firstly,to calculate the energy of non-zero delay simulation waveform,we propose a gate level power calculation method driven by non-zero delay events.Then,considering that the dynamic power integrity simulation requires the instantaneous power during the switch process of the gate unit,we propose a switch current model based on static timing information.The model uses gate-level timing data to model the instantaneous power of the unit,and linearly approximate the instantaneous power.Finally,we complete the corresponding code development,through the simulation test comparison,the error of total power is-6.55%,the instantaneous power waveform is close to the transistor level simulation results,and the simulation efficiency is improved by 284.58 times.