Design And Implementation Of Standard Digital Jitter Generation Module

With the transmission rate between digital systems reaching the Gbps level currently,the stability and accuracy of data transmission at high rates have become an important criterion for evaluating whether the digital system is working normally and stably.Among them,the timing jitter of the digital signal becomes the key factor for data correct delivery at high speeds.This thesis is based on the researches of "Quick Extraction of Digital System Jitter Features and Jitter Generation Correction Methods and Technology" and "Timing Data Generator".It requires generating various types of jitter with controllable amplitude and frequency into the data pattern.On the basis of jitter theory,research how to accurately generate jitter components into the data pattern to meet the jitter performance test of highspeed digital systems in the modern digital signal field.This paper mainly studies the following aspects:(1)Analyzed the characteristics of digital signal jitter from time domain,frequency domain and statistical domain,and combined with the research index requirements and technical difficulties,targeted the digital signal's timing jitter converted from amplitude noise to in the digital system,and the timing jitter caused by crosstalk,reflection or other signal integrity issues the circuit is analyzed to reduce the undesired jitter introduced by the jitter generation module itself.(2)Researches the principle on the analog modulation based jitter generation method and the VCO based modulation jitter generation method,the design of related circuits and the construction of related platforms for testing,and combined with the subject index requirements,the problem of coupling between the jitter amplitude and frequency And the circuit itself introduces excessive random jitter noise to analyze the reason.(3)Propose a digital jitter generation method based on digital synthesis and DTC digital time conversion technology and design related circuits,and realize the generating sine,square,triangle and Gaussian noise jitter to the data pattern of 10MHz?2Gbps data rate required by the project index.The frequency coverage of jitter is 0.015Hz?1.56 MHz,and the amplitude coverage is 30ps?16.5ns,and it can realize the function of adding jitter to all patterns of some patterns under the gating signal.(4)Starting from the power integrity and signal integrity,research how to reduce the jitter and noise introduced by the circuit itself through design improvements to meet the project index requirements.Generate the minimum 30 ps amplitude of jitter to the Gbpslevel data pattern to ensure the generation The jitter is not overwhelmed by the undesired jitter caused by factors such as noise or crosstalk,and the generated jitter is standardized.