Research On Analog-to-Digital Converter Design In CMOS Image Sensor

With the development of CMOS technology,CMOS image sensor has become an important module for image acquisition because of its excellent performance.As the core module of the CMOS image sensor readout circuit,the analog-to-digital converter's performance has become a key factor that restricts the image sensor's acquisition rate and imaging quality.Therefore,the research on the analog-to-digital converter design in the CMOS image sensor is very necessary.Relying on the national key research and development plan "High-sensitivity,high dynamic range micro-optic device pixel array design" and basic scientific research "XXXX platform technology research",in order to improve the imaging quality and frame rate of CMOS image sensors,and reduce power consumption,this paper conducts research on the analog-to-digital converter design in the image sensor.The main research contents of this paper include:Firstly,a column-level analog-to-digital converter is proposed based on 0.18?m CMOS process.The analog-to-digital converter adopts a single-slope structure,and introduces a low-offset rail-to-rail comparator based on intelligence optimization algorithms.The rail-to-rail design increases the quantifiable range of the circuit,and the offset calibration of the comparator improves the accuracy of the circuit.According to the structural characteristics of the column-level analog-to-digital converter in the CMOS image sensor,while ensuring the normal operation of the comparator,an artificial intelligence optimization algorithm is used to optimize the power consumption of the comparator,thereby reducing the power consumption of the CMOS image sensor.Under the condition of TT corner and 27?,input a 19.34 k Hz sine signal,the sampling frequency is 38.91 k Hz,the ENOB is 9.72 bit,and the SNDR is 60.8d B.Secondly,in order to solve the problem of slow quantization speed and long period of the column-level single-slope analog-to-digital converter,a pixel-level two-step slope analog-to-digital converter is proposed,which divides the quantization process into two step,and the original quantization needs to be completed once 1024 clock cycles reduced to 64 clock cycles.By modifying the ramp generator,it can generate two ramp signals with different slopes and opposite directions;only one sampling capacitor and several switching circuits are added before the comparator,which can make the comparator complete the comparison function and at the same time complete the addition operation of the analog signal;the data processing module is used to calibrate the error of the final output digital code of the circuit to improve the accuracy.Under the condition of TT corner and 27?,input a 95.83 k Hz sine signal,the sampling frequency is 195.08 k Hz,the ENOB is 9.25 bit,and the SNDR is 61.2d B.Finally,the layout design of the two proposed analog-to-digital converters is completed.According to the different positions of the two circuits in the image sensor,different layout methods are used to design the circuit layout.When designing the layout of the column-level analog-to-digital converter,the layout width is reduced to facilitate integration;when designing the layout of the pixel-level analog-to-digital converter,the pixel size and fill factor are ensured.