Performance Optimization For Parallel Systems With Shared Dwm Via Retiming,Loop Scheduling,and Data Placement

Domain Wall Memory(DWM)as an ideal candidate for replacing traditional memory especially in parallel systems,has many desirable characteristics such as low leakage power,high density and low access latency.However,due to the tape-like architecture of DWM,shift operations of accessing data have vital impact on latency performance.Considering data-intensive applications in parallel systems with massive loops and arrays,increasing parallelism of loops,along with appropriate loop scheduling and data placement on DWM will significantly decrease the latency and total execution time.This paper explores optimizing performance of parallel systems,in which applications access arrays data,through retiming,loop scheduling and data placement.It proposes Integer Linear Programming(ILP)formulation and Scheduling While Placing(SWP)algorithm to generate optimal or nearly optimal loop scheduling and data placement with minimum execution time.The experimental results show that SWP and ILP can effectively reduce execution time by 63.4% and 70.6% when compared with greedy List Scheduling First Access First Place(LF)algorithm.Besides,this paper proposes Threshold Retiming Repetition(TRR)algorithm to combine retiming technique with SWP or ILP algorithm.The experimental results show that SWP+TRR and ILP+TRR can further reduce the execution time by 70.7% and 72.5% when compared to results without retiming.