Research And Application Of Key Circuits Technology For High Energy Efficiency MRAM Read And Write

With the scaling down of CMOS process,the static power of integrated circuit is continuously increased and its operation frequency is limited by interconnect.Static power can be eliminated by using non-volatile cache and working memory.MRAM is selected of one of the proper candidate for next-generation non-volatile memory.However,it has several problems,e.g.,low TMR,high temperature induced TMR degradation,as well as read disturbance due to low sensing current,which lead to low probability of MRAM sensing and in-memory-computing(IMC).The realization of high energy-efficiency MRAM sensing amplifier(SA)and IMC method shows significant issue.Firstly,high margin,speed and stability(HMSS)SA with current mirror was proposed to enhance current margin twice of the traditional CSA.Besides,a triple sensing margin SA(TM-SA)was implemented to dynamically trade-off the margin between reference and data bit-cell,which improves the margin between the other reference and the data cell.The current margin achieves three times that of the traditional CSA.Then,a pipeline voltage-mode SA(PVSA)was proposed to alternately use charge/discharge phase,which achieves single bit-line charging in two read cycles.Finally,four types of MRAM based in-memory-Boolean logic was realized with a novel writing mode by using two emerging MRAM devices.Using SMIC 28-nm CMOS process,the proposed HMSS shows improved sensing probability than previous SA implementations by more than 3%,when TMR is reduced to50%.TM-SA is taped-out using 14-nm Fin FET process in 1Mb MRAM chip.When TMR is reduced to 40%(90% in others),its failure probability is increased to more than 10%.With TSMC 28-nm process,the energy consumption of the proposed PVSA was reduced by 48%compared with traditional VSAs.Among the proposed four kind of write-mode IMC,the SOT mode IMC owns the optimal power(0.784?W),and the VCMA+STT mode IMC owns the optimal delay(1.19ns).