The Design And Study Of A Disaggregated Data Center Network System

The vigorous development of big data and cloud computing has caused the explosive growth of network traffic,which brings performance and overhead challenges to data center networks.How to provide low-latency and high-bandwidth performance for mixed workloads has become the focus of data center network research.The traditional data center network is constructed with a server-centric architecture.The unit of deployment and operation in datacenters is a monolithic server,and the number of various resources in the monolithic servers is fixed and deployed in one machine.Therefore,the data center of the monolithic architecture has an inefficient resource utilization,coarse failure domain and bad support for heterogeneity.The disaggregated datacenter breaks monolithic server into disaggregated,network-attached hardware components,which can effectively solve the above problems.At present,most of the research work on disaggregated datacenter has designed new network topologies for it.However,instead of proposing a completely new networking system for resource disaggregation,we expanded the existing network by adding new resource nodes into the network and keeping the original structure of switches.It will have both the advantage of classic topology and the additional benefits of resource disaggregation.The purpose of this thesis is to design a disaggregated data center network topology in view of the problems in the monolithic architecture,which can simultaneously meet the performance requirements of workloads with different delay sensitivity and save hardware resources as much as possible.The design of this article is to organize the decomposed computing nodes into a basic network according to the Spine-Leaf topology,use a switch to connect all the memory nodes required in the network,and connect this switch to the core switches of the Spine-Leaf topology to realize the interconnection between computing nodes and memory nodes.We have found that if the network downstream bandwidth becomes a bottleneck when the memory resources are sufficient,the data packets of the memory access flow usually suffer severe queuing delay on the out queue of the port.Therefore,in order to eliminate the bandwidth bottleneck in the network,we choose to use a multiport switch to connect the memory node,establish multiple links between this switch and each core switch,so as to reduce the congestion in the network and reduce the queuing delay of packets.We use a network simulator to construct and evaluate the network topology designed in this article.We use several different types of real application data as the experimental workload.We evaluate the topology based on the mean flow completion time and the number of memory nodes required.It proves that the disaggregated network topology designed in this thesis can better meet the performance requirements of applications with different delay sensitivity while saving hardware resources.