Research On Negative Capacitance Junctionless Field Effect Transistor

Integrating ferroelectric materials with negative capacitance effect into the gate of a traditional junctionless field effect transistor(JLFET)can form a negative capacitance junctionless field effect transistor(NC-JLFET).After the concept of NC-JLFET was proposed,it has become a research hotspot in the field of microelectronic devices,because it can not only overcome the bottleneck of the ultra-steep abrupt junction in the chip manufacturing process,but also achieve a lower operating voltage,so as to solve the unsustainable continuous shrinkage and serious heating problems of the chip.This paper mainly focuses on the in-depth exploration of the structure and mechanism of NC-JLFET,and uses TCAD tools to simulate and describe its electrical characteristics.First,this paper gives the specific working mechanism of junctionless transistors from the perspective of energy band,and analyzes the ferroelectric capacitor model and surface electrostatic potential model of negative capacitance junctionless transistors.Secondly,through the Sentaurus TCAD tool and according to the corresponding physical model,the negative capacitance junctionless double gate transistor was designed and simulated,and the different electrical characteristics of the negative capacitance junctionless double gate transistor and the traditional JLFET were compared.The results show that NC-JLFET has the characteristics of steep sub-threshold swing lower than 60 m V/decade and low operating voltage,and its influence on the electrical characteristics of the device is analyzed from the aspects of ferroelectric thickness,spacer,doping concentration and temperature.Then,this paper studies the Simulation/RF of NC-JLFET,and through small-signal simulation analysis,it is confirmed that it is superior to traditional JLFET in terms of transconductance and output conductance.In addition,the simulation results also found that in terms of cut-off frequency and maximum oscillation frequency,NC-JLFET can reach the same maximum value at a lower gate voltage,verifying that the device is suitable for low-power circuit applications.Finally,this paper analyzes the performance of a negative capacitance junctionless Fin FET transistor with a tri-gate structure,and proposes the best choice for the device in terms of ferroelectric thickness,ferroelectric material parameters,spacer and gate dielectrics,so that the performance is optimal.Negative capacitance junctionless transistors are expected to become low-cost and low-power devices in the field of IOT in the next generation of integrated circuits,so the research content in this paper has a good guiding significance for the design and optimization of NC-JLFET devices.