Research Of Pipelined Belief Propagation Polar Decoder

Due to the unique channel capacity-achieving property of polar codes,it has attracted much attention in the coding and industrial fields in recent years,Successive cancellation(SC)algorithm and belief propagation(BP)algorithm are two typical decoding schemes of polar codes.SC decoding is implemented by recursive method,and its decoding structure is simple and has low complexity.Compared with SC,BP decoding has high parallelism,can provide a higher throughput and lower decoding latency.However,the existing BP decoders generally have the problems of low utilization of functional units and high memory resources,resulting in the hardware performance of the decoder still not ideal,so further improvement and optimization are needed to improve the competitiveness of BP decoder in practical application.The work of this paper mainly focuses on the optimization of BP decoder and its hardware implementation.The specific work is as follows:Firstly,the existing design schemes of BP decoder are analyzed and compared from the number of basic computational block(BCB),the utilization rate of BCB and decoding latency,by studying the approach of message propagation and scheduling strategy of BP decoder in the iteration process.Based on folding technology and pipelined architecture,a new update scheduling method called new and old value(NOV)scheme is proposed in decoding process via using new-value(NV)and old-value(OV)strategies.The theoretical calculation shows that decoding latency of one iteration can be reduced by 50.7%and the utilization rate of BCB can be increased by 50.6%compared with the existing pipelined partially parallel BP decoders under different code lengths and without hard decision.Secondly,according to NOV scheduling scheme,this paper presents an architecture of BP decoder based on NOV,which consists of BCBs,memory module,hard decision module and commutation module.Through the formulation of specific quantization scheme and memory scheme,hardware overhead can be further reduced,and functions of the core modules of the decoder,such as BCB and memory module,are designed and implemented on the FPGA.Simulation and synthesis show that when polar code parameter is(1024,512),the selected quantization scheme is(1,8,3),and the scaling factor is 0.9375,compared with the existing pipelined partially parallel BP decoder,the proposed NOV BP decoder will lose 0.1 dB decoding performance at BER of 10-3,but the consumption of memory resources(registers&block memory)can be reduced by 25.8%to 38.9%,and the frequency can be increased by 1.9 to 2.1 times with the same number of BCBs.