Research And Design Of Interrupt System In RISC-V Architecture

With the development of IC industry,the research and development of chips have caused highly attentive.Technologies of microprocessors design are the most significant part in IC industry,but we always faced the problem that independent research and development are weak,and independent intellectual property rights have been in some developed countries for years.In this case,it seems difficult to develop the local IC industry.RISC-V(Reduced Instruction Set Computer-Five),an open source instruction set architecture developed by the Berkeley team,has received widespread attention and offered us the opportunity to use,due to its open source and advanced nature.Research and development of microprocessors based on RISC-V has become an inevitable new trend,opening a new way for us to achieve independent research and development of chips.Interrupt technology is an important part of the processor design.It not only can accelerate the processing efficiency of the processor but also enhance the real-time reaction of events.Meanwhile,it can achieve communication between processors in multi-core chips.The definition of RISC-V privilege architecture easier the implementation of the hardware design of the interrupt mechanism.This article focuses on the implementation of the interrupt system based on the RISC-V,analyzes the implemented of interrupt mechanism with RISCV architecture and discusses the processing of interrupt processing from hardware to software in details.This paper outlines the relevant work about the research of RISC-V,and elaborates the knowledge in RISC-V ISA which used to design the interrupt system.Then divided the interrupt system into two parts: the interrupt controller and the interrupt processing unit which belong to the processor.According to the type of interrupts,we sort the interrupt source into external interrupts,software interrupts and debug interrupts.Each of interrupt handled by the corresponding controller.Debug interrupt is the special one,the debugging mechanism architecture document is mainly used to implement the communication between the host and the processor by using the software debugging.The interrupt processing unit belongs to the control module,and it receives the interrupt request from the interrupt controller and the abnormal request inside the processor,to make corresponding processing and generate control signal for the processor.Interrupt priority selection,interrupts flags,interrupt response mechanism,debugging interrupt handling mechanism etc.are supported in the interrupt processing unit.The real-time operating system requires immediately response to abnormal interrupts,we discussed two classic method to design the interrupt response mechanism.Simulation results show the interrupt vectorization mechanism has faster response time,and it was finally selected.Finally,the RTL code of the interrupt controller and internal processing part implemented in the project are simulated and analyzed.The 0.13 um process library of SMIC is used for logic circuit synthesis.At the end of the project,we designed interrupt handlers for different interrupts and abnormal events as a reference in the study of interrupt mechanism.This article focuses on the implementation of the interrupt system based on the RISC-V,implements the hardware implementation and simulation with five-stage pipeline in Verilog,and tests the system with standard instruction test provided by RISC-V official tool chain.The test results show that the design can support the handling of interrupt and exceptions.What's more,the implementation of the debugging mechanism contained in the interrupt system.Verification in system-level shows the design accomplished the communication between the host and the processor.Finally,this project implements a complete interrupt mechanism,which also meets the real-time and flexible requirements.