Design Of RS(544,514)Encoder And Decoder For High-Speed Optical Communication

In 2014,IEEE 802.3bj defined the 100Gbit/s Ethernet standard.With the increasing transmission speed of optical communication,the requirement of error correction ability is higher and higher.As a classical linear block code,RS code has superior error correction ability.IEEE 802.3bj standard defines two kinds of RS codecs,which are RS(544,514)and RS(528,514).The forward error correction method can solve the problem of coding transmission and error correction in 100Gbit/s Ethernet network.In this paper,we investigate the literature of RS code,and find that most of the existing research results about RS code are n=255 code length,and few of the research results about RS(544,514)-FEC codec are reported.This paper refers to the concept of RS(544,514)-FEC codec proposed in the standard,designs RS(544,514)-FEC codec,verifies the algorithm with C language,and designs the hardware circuit with Verilog and simulates the logic function correctly.At present,the traditional RS encoder circuit needs a long time delay.In this paper,the traditional serial RS(544,514)coding circuit is designed and synthesized with saed28nm library.From the comprehensive results,it can be found that the circuit performance is poor,and the data throughput is only 4.99Gbit/s,this article refers to IEEE 802.3bj RS(544,514)code encoder,the traditional encoder circuit is recursively parallelized.One clock cycle can process the data of four clock cycles of the traditional encoder.From the comprehensive results,we can see that the clock frequency 434.78Mhz,data throughput is 17.39Gbit/s.8-way parallel can meet the requirements of 100Gbit/s optical network communication application.In this paper,the RS(544,514)decoder circuit is designed.Based on the decoding function,this paper focuses on the key equation solving module,which is the most important module of RS(544,514)decoder.At present,there are two ways to solve the key equation,one is BM algorithm and the other is Euclidean algorithm according to BM algorithm.In this paper,BM algorithm,IBM,Ribm algorithm circuits are designed.The hardware resources of Ribm circuit meet the requirements of traditional Ribm algorithm.After simulation,the function is correct,the working frequency is 83.3mhz,the throughput of a single decoder module is 13.33gbit/s,and the 8-way parallel can meet the requirements of 100Gbit/s optical network communication application.The RS(544514)codec designed in this paper can correct the transmission errors correctly.The encoder circuit can be applied to 100Gbit/s optical network.For RS decoding,its Ribm algorithm also meets the requirements of hardware resources in the current literature.