Research On The Reduction Of The On-Resistance Of The Low Voltage Trench Power MOSFETs And The Optimization Of Its Manufacturing Process

Power semiconductor devices are the core and foundation of power electronics.The trench power MOSFET adopts the longitudinal layout,which has the characteristics of lower on-resistance compared with other MOSFET devices,and the switching loss is very small in the work.With the improvement of performance of trench power MOSFET devices,the field of application is gradually expanding.Therefore,it is of great practical value to study the optimization technology of on-resistance of trench power MOSFET devices.In this paper,the optimal reduction of low voltage trench power MOSFET on-resistance is achieved by two methods: cell pitch shrink and substrate resistivity reduction.The new BARC technology overcomes the limit of exposure lithography tool,lithography micro trench successfully to0.2?m device on-resistance is reduced by 4.1%.In addition,study on the reduction of substrate resistivity to reduce the impact of device parameters,through the method of EPI layer thickness increases 0.2?m,improve the resistivity decrease of the breakdown voltage is decreased,and the on-resistance of the device is reduced by 6.7%.At last,the total resistance of the device is reduced by 10.9% with the two schemes mentioned above.This paper also studies and optimizes the problem of device test parameter anomaly in the process of manufacturing.The threshold voltage of the device leads to high and discrete problems by the distance decrease between the contact hole and channel,using silicon oxide added 0.05?m thickness as spacer,transverse trench CD reduced by 0.08?m,the threshold voltage is reduced by 12.3%,dispersion decreased 64.6%,to solve the problem of abnormal threshold voltage device.At the same time,analysis of the low yield of the chip,found by the unstable source layer lithography process caused by device drain leakage,through the source layer layout extend 0.1?m to the cell and the CD bar CD change from 2?m to 0.6?m in the new design,wafer yield increase 7.5%,CD bar CD wave is less than 10%,expand the source layer lithography process window.The above two process optimization schemes are integrated,and the final product of the new technology has successfully realized the production of mass production.