The FPGA Implementation Of Data Selecting After Sorting And Encryption Algorithm

Sorting algorithm is widely used in scientific fields like phased array radar,image processing,search engines and so on.For example,in the radar signal processing system,various sorting algorithms are used to calculate false alarm probability to improve the calculation accuracy of the whole system.In median filtering algorithm,which is always used in image processing,a sorting algorithm is often used to obtain a better final image effect.And,in the logistics,search and other fields,there is also a fuzzy sorting algorithm to make the best decision.With the development of integrated circuit design,now FPGA provides a more powerful hardware implementation platform for digital circuit design.In this paper a number of signal processing modules are designed and implemented basing on the FPGA platform,and the corresponding tests and verification are carried out.Specific work is as follows:1)This paper mainly designs a sorting and selecting modules working on an FPGA platform with a flexible and configurable framework.We can choose different architectures for the module by configuring two static parameters.We may select the Ping-Pang architecture,which has the best data throughput.Or,we may choose the architecture with only one comparator,which occupies the minimum resource.Also,we can get a compromise and get the grouping comparator architecture.By configuring the static parameters of the top layer,we can also choose the limitation of the picking number as well as the number of comparators used in the module.This can increase the applicability of the module,and increase the scope of the use of module.The Ping-Pang architecture avoid back pressure for incoming data by grouping the incoming data into two groups,Ping and Pang.Architecture with single comparator uses the only comparator to read data from the RAM and write the selected data into it after comparison.The grouping comparator architecture make a compromise between resource and data throughput by using a group of comparator.2)We also study two data encryption algorithm,namely AES and Camellia.After learning the encryption and decryption process of the algorithms,we design modules to accomplish AES and Camellia on FPGA.We make some optimization on the hardware architecture after fully studying the workflow of the algorithms,and we get better synthetic results and running results.3)In this paper,all the modules designed are verified in detail,including functional verification and performance verification.We set up the simulation platform of MATLAB and Modelsim.,design code source excitation.In order to fully verify the function of the designed architecture,we design code source excitation combining the actual application scenarios of the module.The sorting selection module,which has been validated on Xilinx's V7-980 chip,is already running on the actual radar system.