| Recently, NAND flash memory has been widely used in the embedded market because of its desirable properties such as non-volatility, shock resistance, low power and low latency for reading and writing. As a result, solid state drive (SSD) based on NAND flash memory chips becomes popular in the consumer electronics market because it is tough on shock and its I/O performance is better than that of conventional hard disk drive. However, as the density of the semiconductor grows higher, the distance between its wires narrows down, their interferences are frequently occurred, and the bit error rate of semiconductor increases. Such frequent error occurrence and short life cycle in NAND flash memory reduce the reliability of SSD, which remains as a critical issue when designing a large-scale flash storage. In light of this, RAID storage architecture is put forward. However, the parity-handling overhead for reliability is significant, especially for sequential parity write on a single parity chip of standard RAID4. On account of this, two ways are proposed to relieve pressure of parity processing here. One is to use multiple parity channels to process parity in parallel. The other one is to utilize the time interval between requests to process parity. Based on previous delayed parity processing scheme, in order to make it more efficient, as long as the time interval of requests is bigger enough to deal with one parity update, the CPU idle would be utilized promptly to process parity data. Via trace-driven simulation, the performance of this parallel parity processing RAID NAND Flash SSD (abbreviation PPP from now on) is evaluated. The experiment results indicate that the performance of RAID4 with trace TPC-C and Exchange is decreased by 28.35% and 29.51% respectively in comparison to non-parity NAND Flash SSD. However, the performance of PPP with two, three and four parity channels for trace TPC-C and Exchange is improved by 7.17%, 3.11%, 5.07% and 7.12%, 6.12%, 4.75% respectively. From another point of view, with the sustained decline of NAND flash price, it is definitely feasible to add more channels in exchange for better performance. Therefore, the creative thought about parallelized multi-channels parity processing in a single SSD will be thoroughly discussed in this paper. Keywords: Parallel Parity Processing, Multiple Parity Channels, Delayed Parity Queue, Processing Capacity in One Channel, RAID4. |
